쉐도잉 연습: Via-in-Pad Reliability: When Does Your PCB Need It? #pcbmanufacturing #pcbdesign - 영상으로 영어 말하기 배우기

Hello everybody, I am Zachariah Peterson.

Welcome back to my channel.

Today I'm going to be answering a viewer question about vias in SMD pads in PCB design.

Should you do it?

Should you do it in bottom terminated components or in any other type of component?

We're going to take a look at that viewer question.

We'll jump into some examples in Altium Designer.

And I'm going to show you some data from the IPC High Density Packaging User Group

that illustrates what can go wrong if you use a Via InPad.

Let's go ahead and get started.

This viewer question comes from one of our design review videos entitled ESP32 Design Overkill.

You guys know how much I have a love -hate relationship with ESP32.

And this question comes from WoWOWEWAH2203.

Nice username.

in general will finish off the PCB by covering the via through holes.

In addition, packages are just getting harder and harder to completely fan out with smaller pitch.

Our team has no choice but to use more expensive blind and buried vias now due to the package on LPDDR5s.

There are a few different dimensions to this question.

So first of all, most PCB manufacturers will leave your vias untented tent the vias.

If your PCB manufacturer is taking your design that doesn't have tented vias and is just tenting them anyways, you need to find a new manufacturer.

Your manufacturer should produce the board based on the data that you give them, not the data that they want to put into the board.

The second point I would like to note regards the manufacturing capabilities for via in pad.

The manufacturing capabilities have not been a problem for quite a long time.

Now, manufacturers will recommend to people to not put the vias in pad vias in pad, I think because a lot of people will just put via in pad

and then they won't think about whether or not they need to have it plated and filled or capped.

So if you are going to use via in pad, you need to make sure that you use it correctly.

If you put vias under SMD pads, make sure that you specify a conductive or non -conductive fill and then specify whether you need it planed over and planarized.

Now, if you are using a high density no choice but to use via in pad.

And that means you are going to have to specify filling and capping and plating over.

What I want to do now is hop into Altium, we can take a look at some designs that need via in pad, we'll see how to use it correctly.

And then we'll take a look at some reliability data for via in pad.

So you can understand the risks of using via in pad in your designs.

Now the first design that I want to look at is our Ethernet switch project that we did for all the

and you can see in this Ethernet switch we have three BGA components.

We have the main Ethernet switch controller here on U1, we then have an expansion PHY over here on U3,

and then U5 is a DRAM chip.

So if we put this into 2D, we can zoom in and we can see what type of design we're working with here.

So this is a design that does not require via in -pad.

could use via in pad if we wanted and we could use blind

and buried vias if we wanted to

but in this design we're not required to the reason for

that is of course if we just take a look at the pitch on these pads

if i can get my snap to work correctly

if we just take a look at the pitch on these pads you'll see here

that the pitch is one millimeter and of course we're able to fit an 8 via.

Even if we go over to this a little bit denser BGA for this DRAM chip,

you'll see here that if I measure the spacing between the pads on the DRAM chip, this is 0 .8 millimeters and the pad and via

that we have for this fanout is an 8 mil drill with a 16 mil pad.

So again we're still able to use the dog bone pitch.

Now what about a design where we're going to need via in pad?

Well at some point the pitch on these BGAs become

so small that we have no choice

but to put a via directly in the pad and that's

because of course as we collapse the spacing between these pins you will see here

that there's not going to be any room for this via in between these pads.

And so an example is shown here in one They are using the NRF 52 in the VFQFN package.

It has a 0 .5 millimeter vertical and horizontal pitch between these pins.

And as you can see here, we have vias placed directly into the pad.

Now, of course, if I were to try to put a via in this region, even with a 12 or 14 mil pad size, it just is not going to fit.

You have no choice but to put it directly in the pad.

Now, this is just for the BGA.

could do via in pad elsewhere in the design if we really wanted to.

But in this particular design, you can see here that the rest of the components are not super high density.

They're not super small components.

We don't have a bunch of zero two zero ones or zero one zero zero five passives on here.

And so in that case, we don't have a requirement to put the vias in pad on the rest of the design.

You can see here that we have one component right here, just a capacitor where one of the vias is in the pad

that is acceptable because these vias in the fabrication notes for this design are going to be filled

and capped so because of

that it is still acceptable to put these vias in pad like you see here on this capacitor

and like you see here underneath this nrf52 package.

So now we've seen what kinds of designs might need via in pad,

and we even see that you can use via in pad in cases where you don't necessarily have a high density BGA.

But when you do have a high density BGA, there are, of course, reliability issues that can arise.

And this has been studied pretty extensively by the IPC high density packaging user group, as well as PCB vendors and independent researchers.

So let's take a look at some of that data right now.

that I'm showing in these slides has been presented in some other videos

and I'm gonna link to some of these other videos in the video description

but for now what I want to do is just kind

of run through some of these BGA via in pad defects

that can arise during PCB assembly as well as after deployment in the field

so first head and pillow is an assembly defect where you have incomplete wetting and side of the BGA,

basically leaving a contact here between two separated balls of solder.

And of course that can lead to an intermittent short.

Here voiding occurs where you have voids that form in the solder ball, and you can even see here

that we have some via -in pad where some of the solder does adhere to the copper pad on the PCB,

but the void allows a crack to form along the bottom side of this ball.

leads to an intermittent failure.

Here you can also have a failure of the via -in pad itself,

where the cap essentially gets absorbed into the ball while the ball is molten, and that creates a failure of the via -in pad.

And then you can also just have ball fracture, where essentially you have repeated thermal cycling,

the solder ball on the bottom side of the package gets fatigued, and then eventually a crack forms, and then you get a fracture.

via in pad when we have via in pad we want to make sure

that we prevent some of these defects

and one way to help prevent some of these defects is to ensure planarity of the pad arrangement in

that BGA footprint now planarity can get affected due to dimples in the via in pad plating over process

so when you have a via in pad you then fill it

and cap and plate it the plating can form a and that dimple can then create some non -planarity.

Now on a small case passive, like for example a 0603 capacitor or 0805,

100

those kinds of passives, probably not a big deal.

101

And on smaller BGAs with low pin count, also really not a big deal.

102

that non -planarity can create a lot of distortion in the

103

contact between all of the balls on the bottom side of the package and the pad in the PCB footprint.

104

And that could potentially lead to some of the issues that we saw in the previous slide.

105

So given all of these potential problems where you have a ball

106

that could get fractured or you have non -planarity leading to open circuits or leading

107

reliability of these different types of leadless packages where you can use via in -pad.

108

Well, the IPC High Density Packaging User Group has done some studies on via in -pad in BGAs as well as QFNs.

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And so what I'm going to do now is show some reliability data for three different types of packages, a BGA 192 package, a ceramic BGA package,

110

basically where the substrate of the BGA package is a ceramic material.

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and a QFN package on a six layer PCB.

112

Now the microvia aspect ratio on all of these packages is less than one, which is going to be considered a highly reliable microvia.

113

Now these samples were thermally cycled and then they looked at the failure rate in each of these different package types.

114

So first let's look at the reliability data for the QFN package compared to the ceramic BGA package.

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So here what you're seeing in these plots,

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plots and we're comparing the lifetime of these microvias for cases where we have via -in -pad versus no via -in -pad.

117

And what you're seeing here for the QFN is

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that the QFN package with via in pad has approximately a

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12 % shorter lifetime than the QFN package without via in pad.

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Now eventually these two curves overlap and they have the same lifetime after you do enough thermal cycles,

121

which is exactly what you would expect after repeated thermal cycling.

122

in pad has similar lifetime as the ceramic BGA package with the via in pad.

123

So I think this is a little surprising because when we talk about reliability of via in pad,

124

we might expect that the via in pad reliability doesn't really depend on the package type

125

and the data just shows that that isn't true.

126

Next, let's compare the BGA 192 package with the ceramic BGA package.

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So again, the ceramic BGA package without the Via N -Pad and with the Via N -Pad have similar lifetimes,

128

but when we compare the BGA 192 package with the Via N -Pad versus BGA 192 without Via N -Pad,

129

we see very clearly that longer lifetime in this BGA package with no via in pad.

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So again you can use via in pad if you like, but this is one of the risks that you run into.

131

And using via in pad is going to give you different levels of reliability depending on the package that you're working with.

132

So again QFN is going to show a slightly lower lifetime,

133

but with a BGA 192 package which has an organic FR4 substrate,

134

it is going to have a much lower lifetime than a ceramic BGA package.

135

Some further data from the IPC High Density Packaging User Group shows a few important points.

136

So number one, failures tend to most commonly arise near the corner balls in the BGA package.

137

That actually makes perfect sense because if you have any level of non -planarity

138

that could be thermally induced or it's influenced by the presence of dimples in the via and pad process, distance

139

and that's exactly why you would expect these failures to be

140

more common in the corner balls of the package rather than in the center balls of the package.

141

Now let's look at the data in the table in the bottom half of this slide.

142

Here in this table what they're looking at ultimately is the number of components

143

that do not show voiding in the corner solder balls

144

and what you can see in the ceramic BGA package is

145

that after thermal cycling all of the components show voiding the corner solder balls.

146

So basically all of those solder balls are going to be at risk of failure from further thermal cycling.

147

Now what about the BGA 192 package with via in pad and no via in pad?

148

Well here you can see a very large difference between the via in pad case versus the no via in pad case.

149

Only one of the components does not show voiding compared to 24 of the components showing

150

via -in pad component with the BGA 192 package shows many more failures.

151

Now what about a smaller BGA, for example, an 84 pin BGA with via -in pad versus no via -in pad?

152

Well, again, the via -in pad package shows more failures, but still fewer failures than the larger BGA.

153

And again, this is what we would expect with voiding that arises in the corner balls of the package.

154

If you have a physically you're going to be at more risk of voiding and failure at the via -in pad because,

155

again, that deformation accrues over distance.

156

So that's exactly what the data shows us here.

157

Now, reliability is clearly related to two things.

158

Number one is the size of the package, and then number two is the materials used to make up the package.

159

That's why we see the difference between the BGA -192 component and the ceramic BGA component.

160

I guess there's a third part, process, but really the package matters as well.

161

To help ensure reliability of BGA packages,

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PCB assemblers have done a really great job of planning their processes to ensure that the number of reflow cycles is minimized.

163

Also, newer materials are available that have a closer coefficient of thermal expansion match to the coefficient of thermal expansion for copper.

164

So these newer materials are enabling much higher density packages and PCBs.

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Some of the material vendors for example, AGC.

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They produce a new resin coated copper that has a low CTE.

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And Paul Cook, one of the podcast guests, was actually at a recent SMTA event on UltraHDI talking about some of these materials.

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So I will probably have Paul back on the Altium OnTrack podcast to discuss this more.

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And I might even have a conversation with him on my channel.

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So make sure to subscribe to Altium Academy and this channel to stay tuned for that content.

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on this channel and on the Altium Academy channel.

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And of course, if you ask a great PCB design question, it's probably gonna end up in one of these videos.

173

Make sure to hit that like button, hit the subscribe button, and I'll see you next time, everybody.

174

Thank you.

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이 비디오는 기술적인 주제를 다루는 대화에서 명확한 논리 전개와 전문 용어의 자연스러운 사용을 연습할 수 있는 좋은 기회입니다. 특히 "via in pad"와 같은 전자 공학 용어를 포함한 긴 문장을 말할 때, 흐름을 끊지 않고 발음하는 능력을 키울 수 있습니다. 영어 쉐도잉을 통해 빠른 속도의 대화에도 따라갈 수 있는 리듬을 익히고, 전문 용어의 발음을 정확하게 연습할 수 있어요.

재사용 가능한 표현 모음

"Should you do it? Should you do it in..." – 의문문을 연속으로 사용해 논점을 강조하는 표현
"We're going to take a look at that viewer question." – 시청자 질문에 대해 다룰 때 사용하는 자연스러운 표현
"There are a few different dimensions to this question." – 문제의 여러 측면을 언급할 때 유용한 구문
"The reason for that is of course..." – 원인을 설명할 때 자주 사용되는 연결 구
"What about a design where we're going to need..." – 새로운 주제로 전환할 때의 자연스러운 표현

약점을 고치는 연습법

이 비디오의 대화는 빠른 속도와 복합 문장이 특징이어서, 쉐도잉을 할 때 주의해야 할 부분이 많습니다. 특히 "manufacturing capabilities have not been a problem for quite a long time"와 같은 긴 문장에서, 단어 사이의 연결음(linking)과 리듬을 따라가는 것이 중요해요. shadow speak 연습을 할 때는 먼저 비디오를 느리게 재생하며 단어별로 발음을 확인하고, 점차 원래 속도로 따라해보세요. 또한 "via in pad", "blind and buried vias"와 같은 전문 용어의 발음을 정확히 익혀서, 기술적인 대화에서도 자신감 있게 말할 수 있도록 연습하세요. 유튜브 영어 공부를 할 때 이런 전문 분야의 비디오를 사용하면, 일상 영어뿐만 아니라 전문 영어 실력도 동시에 향상시킬 수 있어요. 매일 10분씩 shadow speech 연습을坚持하면, 빠른 속도의 대화에도 자연스럽게 따라갈 수 있는 능력이 길러질 거예요!

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문형	영상 속 표현
현재완료 have/has + 과거분사 — 과거의 일이 지금도 관련이 있을 때	have tented · have not been · we've seen
수동태 be + 과거분사 — 누가 하는지보다 무슨 일이 일어나는지에 초점	is shown · be filled · has been studied
관계절 who / which + 절 — 사람이나 사물에 대한 추가 정보	one, which is · package which has

쉐도잉이란? 영어 실력을 빠르게 키우는 과학적 방법

쉐도잉(Shadowing)은 원래 전문 통역사 훈련을 위해 개발된 언어 학습 기법으로, 다언어 학자인 Dr. Alexander Arguelles에 의해 대중화된 방법입니다. 핵심 원리는 간단하지만 매우 강력합니다: 원어민의 영어를 들으면서 1~2초의 짧은 지연으로 즉시 소리 내어 따라 말하는 것——마치 '그림자(shadow)'처럼 화자를 따라가는 것입니다. 문법 공부나 수동적인 청취와 달리, 쉐도잉은 뇌와 입 근육이 동시에 실시간으로 영어를 처리하고 재현하도록 훈련합니다. 연구에 따르면 이 방법은 발음 정확도, 억양, 리듬, 연음, 청취력, 말하기 유창성을 크게 향상시킵니다. IELTS 스피킹 준비와 자연스러운 영어 소통을 원하는 분들에게 특히 효과적입니다.

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