跟读练习: A Brief History of Semiconductor Packaging - 通过视频学习英语口语

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In this video, we're going to look at a brief history of the semiconductor packaging industry.

Packaging refers to the integrated circuits, carrier, and enclosure.

It protects the silicon dye inside from physical damage while also allowing it to be connected to other devices.

The industry has long been chopped liver, overshadowed by the sexier work of wafer fabrication.

But it's important and we should know about it.

Let's go.

But first, let me talk about the Asianometry Patreon.

Early Access members see new videos and selected references for them before the release of the public.

It helps support the videos and I appreciate every pledge.

Thanks, and on with the show.

ICs are precious little snowflakes.

They need protection from the real world, which is full of damaging influences.

Particles can get in and interfere with operations.

Moisture in the air can cause their metals to corrode.

High temperatures generated during operations can cause the IC to degrade or even fail outright.

Vibrations or jolts can damage the chip's capabilities.

And so on.

The packaging is for protecting from all of these threats.

Let's talk about what's inside.

First, we have your die.

The die attaches to a metal support called a lead frame.

Oftentimes through the use of clips, adhesive or straps.

The lead frame has wires attached to it which connected to the outside world.

These are called bond wires.

And then finally, there is a plastic or ceramic or metal enclosure surrounding the die, the lead frame, and the bond wires.

This whole setup is considered by the industry as only the first level of semiconductor packaging.

The second level refers to the circuit board, and the third and final level refers to the system's final enclosure, like the desktop PC's chassis.

The process of encasing the fabricated die into its level 1 package is referred to as the back -end.

We can further break down back -end processes to two major steps, assembly and test.

Processes differ based on the technology, but here is the vanilla workflow.

In assembly, we start by cutting the dies out of the completed wafer and inspecting them.

After this, we have to put the dies onto the package's lead frame, called die attach or die bonding or die mounting.

Then we attach the very small bond wires to the dies which allow the chip to communicate with the outside world.

This step is called wire bonding and was pioneered by Bell Labs in the 1950s.

After that, we put the die into its ceramic or plastic package to protect it from the outside world.

At the start, this process had to be done manually, making it one of the first things to be outsourced abroad.

Since then, machines have taken over and a swath of new bonding techniques have been introduced.

Discussing them is beyond the scope of this video, but you should know they exist.

Throughout its history, packaging's goals have stayed rather consistent.

Help the IC achieve its full functionality and don't get in its way, be as small as possible, and be as cost -effective as possible.

In the beginning, only military or aerospace companies used semiconductors.

Price was less of a concern than total reliability.

Ergo, most semiconductor manufacturers packaged their dies in hermetically sealed cans made out of ceramic or steel.

This prevented any contaminants from messing with the chip, but there were serious drawbacks.

Ceramics and metal cost a lot.

They were also heavy, which meant that the circuit boards they were attached to had to support all that weight.

This made them heavy, too.

Packaging took a big leap forward with, who else, Fairchild Semiconductor.

When Fairchild started producing their revolutionary planar ICs in the late 1950s,

they packed them in the same TO5 and flat pack packages they used for transistors, just with a few more leads.

We will talk about flat packs a little later in this video.

But first, let us talk about the TO5.

The TO stands for Transistor Outline.

A TO5 kind of looks like a squid.

Basically a metal can and metal lid.

Fairchild's first micrologic chips were accordingly etched in a round shape.

But the TO5's awkward round shape made it difficult to attach onto and arrange on a board, adding to the labor cost.

Worse yet, TO5's limited how much data the chip can take in and push out.

They maxed out at just 8 -10 pins.

Fairchild's new logic circuits needed far more than that.

To5 packaging diluted the IC's advantages and worsened its disadvantages.

With this situation, how were ICs ever going to get to price parity with germanium devices and vacuum tubes?

In response, Fairchild developed two new packaging techniques.

The first was plastic encapsulation.

It sounds fancy, but the way they did it back then was to put the IC die on a ceramic bead

and cover the whole thing with a plastic blob.

This method had some issues.

Plastic can be permeable to certain chemicals, leading to concern surrounding contamination.

And plastic can shrink or grow, depending on outside conditions like heat, inflicting mechanical stress on the chips inside.

However, plopping plastic onto a chip required very little skill.

This meant that Fairchild could outsource his assembly work to cheap manual labor in Hong Kong or South Korea.

One of the first such electronics companies to do so.

Fairchild's second idea would forever change semiconductor packaging.

Fairchild's digital systems laboratory head, Rex Rice, created a new lead configuration for an IC.

The leads were spaced about one hundred thousandths of an inch apart.

The industry term for this measurement is lead pitch and came out in a single line.

You would attach the package to the circuit board using what is called through -hole mounting.

Here, you insert the package's leads through literal holes drilled into the boards.

The holes have large round solder contact areas surrounding them.

After insertion, you solder the leads on the backside to secure them.

The method for doing this was called wave soldering.

Tests found that this new inline packaging system fit all the criteria.

It can accommodate more I .O some 12 to 16 pins at the start.

It simplified the circuit board layout.

And finally, it took less time and skill to assemble.

The inline arrangement was far simpler than the TO5CAN's circle -shaped leads.

Before deploying the product, Fairchild first consulted with customers and end users who did not like the single line arrangement.

However, they would be okay with two lines.

So Fairchild revised the prototype to two rows of inline pins.

Dual inline packaging or DIP.

Introduced in 1965, the simplicity of dual inline packaging cut the cost of assembly by a factor of four.

The industry widely adopted it throughout the 1970s and 80s.

During those 20 years, DIPs held some 80 -90 % market share when measured by value.

However, as the industry moved into the 1970s and the era of very large -scale integration or VLSI, demands for I -O density kept growing.

Some VLSI chips would require as many as 300 leads.

More leads forced the DIPs to grow increasingly large.

DIPs can have 64 or even more leads, but doing so gave them impractically large board footprints.

If trends continued the way they were, the DIP packages would end up being far larger than the dyes themselves.

This invalidates the various miniaturization gains in semiconductor manufacturing.

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In response to this trend, a series of new packages capable of accommodating far more leads emerged.

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The packaging industry's second big revolution.

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This generation of packages was defined not by their shape, but rather how they were attached to the circuit board.

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Surface mounting technology describes a style of mounting packages onto the board using flat patches of solder already on the board.

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Surface mounting had several advantages over through -hole mounting.

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First, because through -hole mounting required you to solder the back side of the boards to secure the DIPs,

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you can only use one side of the board.

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With surface mounting, you can use both.

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This alone increases the theoretical number of packages on a single board by 35 -60%.

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Second, it allowed us to move the leads closer together.

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Or in other words, for a smaller lead pitch.

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This is because you no longer have the solder contact areas around the holes.

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And third, you can use cheaper boards.

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Drilling a hole into a board costs money.

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And there can be up to a thousand holes on a standard board.

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Contemporary estimates found that a surface mount board costs $0 .13 per square inch, while an insertion hole mounting board costs $0 .15.

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Furthermore, the boards aren't peppered with holes anymore, which means they don't need so many layers to maintain their structural integrity.

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Another cost -saving measure.

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Previously all that surface mounting had to be done by hand.

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Which, considering the smaller lead pitches, required a great deal of skill and training.

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This was the primary reason why surface mounting didn't take off at first.

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New automatic machines finally closed the loop on this.

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Manufacturers now use convection heating, hot gas or even infrared heat rays to solder the packages onto the boards.

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Basically ovens.

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The origins of modern surface mounting technology are murky.

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And there isn't one significant inventor or eureka moment.

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I mean, the concept of attaching stuff to a board is not exactly groundbreaking.

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The earliest credible mention is a British patent filed in 1960.

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It describes resistors, coils, and such attached to a printed board using an adhesive.

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The connectors were connected using solder.

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Early adopters in the 1960s included the US military, which used flatpacks for their missile guidance computers.

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The flatpak was a stackable rectangular glass and ceramic package that was surface mounted onto a board.

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The flat pack was invented in 1962 by Yong Tao of Texas Instruments.

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So actually a few years older than the venerable DIP.

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I couldn't find much more about inventor Yong Tao or his life, which is unfortunate.

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In the late 1960s, the Swiss watch industry adopted surface mounting as a way to reduce the number of electronics in their watches.

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They popularized what is called the Small Outline integrated circuit, sometimes also known as the Swiss outline.

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The small outline looks like the DIP and is made from the same molded plastic materials.

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However, it is far smaller.

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A third as high and half as long.

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This was because its 28 gull -wing leads are spaced far closer together.

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Possible again because we are directly mounting these onto the board.

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They are called gull -wing leads because their shape is somewhat reminiscent of seagull's wings.

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Seagulls are birds that steal your hot dogs at the beach.

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In the 1970s, the Japanese electronics industry began adopting surface mounting technology for their car radios, TV tuners, and TV cameras.

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It is likely they got the idea from Europe, Germany, or Britain perhaps.

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By the 1978 and 1980 period,

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the semiconductor packaging industry had started moving towards surface mounting with numerous published articles discussing its use for increasing packing density. In the early 1980s,

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the Japanese revived the old US military flat pack to create

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an updated surface mount compatible version called the Quad Flat Package or QFP.

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With the Quad Flat, we have the leads projecting down and away from all four sides of the square package.

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Depending on their size, the quad -flat can offer anywhere from 20 to 240 leads.

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Pitches shrank to as small as 1 or 0 .65 millimeters.

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You can go guess how many inches that is.

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The quad -flat quickly evolved.

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Pushed along by consumer demands for smaller and smaller consumer electronics, the Japanese industries introduced yet smaller packages like the shrink quad flat package,

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the very small quad flat package, and the thin quad flat package.

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On the other end of the spectrum, new structures outpaced the quad flat on the lead count front.

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People realized that having the leads come out of the sides meant

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that you couldn't use the real estate underneath the package itself.

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So for high lead count devices, the packaging industry revived an old IBM invention, the pin grid array or the PGA.

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First introduced in 1971, the square -shaped pin grid array can handle hundreds of leads on its underside.

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IBM invented the pin grid array for high IO uses in the computer industry.

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Those packages were made from ceramic, which not only made them more expensive but also their circuit boards,

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since those boards had to get thicker to handle the added weight.

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Plastic variants were later introduced.

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Pin grid arrays were invented before the surface mount revolution.

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So a surface mount compatible cousin emerged in the 1980s.

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The ball grid array.

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With these, solder balls are used rather than pins to connect the chip to the circuit board.

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One big disadvantage of the ball grid was that you could not easily visually inspect the solder connections underneath the package.

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X -ray and electrical tests are often used instead, with badly soldered packages removed, reballed, and reapplied.

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Solder ball technology appear in another packaging innovation that popularized at about the same time as the BGA, flip chip.

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This is where the silicon die is flipped so that it faces downwards.

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To build the interconnects, we ditch wire bonding entirely in connect using bumps and balls on the chip's pads.

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Flip chip technology is still used today and offers several benefits.

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First, there is more contact with a heat sink, which dissipates more heat.

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Second, electrical signals have a shorter distance with flip chip interconnects than bond wires.

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Starting in the 1990s, consumers started buying smaller electronics like mobile phones.

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Smaller devices mean smaller components, chips, and packages.

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Space became a premium in a chip package.

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The industry measures this using what is called packaging efficiency, the ratio of the area occupied by the active device.

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the dye.

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In response to this, the packaging industry developed the Chipscale package, which entered the market in the mid -1990s.

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Chipscale packaging is an evolution of the aforementioned ball grid array

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and refers to any package where the bare dye occupies 80 % or more of the total package area.

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Taiwanese OSAT vendors like ASE Group rose up on the back of such ultra compact packages.

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One prominent implementation of this concept is called wafer -level packaging.

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This is where we hook up all the die interconnects before we cut those dies out of the wafer.

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It's not only very cost -effective, but gives you very small packages.

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As I mentioned earlier, the advent of surface mounting technology created a new generation of packages and techniques.

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As Moore's Law slows down, packaging technologies have seen yet another surge of investment, creating what we can call advanced packaging solutions.

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These new packaging technologies now have a much more direct role to play in the system's overall performance.

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Semi -analysis has a fantastic multi -part breakdown on advanced packaging that I think drops the mic on the subject.

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Perhaps the most well -known of these are chiplets.

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This is a variant of what are called multi -chip modules or hybrid circuits or system in packages.

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I did a video about it previously.

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Most prominently, AMD used them to create a disruptively great product.

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One special area of the multi -chip worlds involves 2 .5D and 3D integration.

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These are especially cool.

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2 .5D integration is where we put multiple dies side -by -side on top of an interconnect substrate called a silicon interposer.

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This silicon interposer doesn't have any logic, but is just made up of many embedded interconnects.

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There are a few consumer products using 2 .5D integration today.

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For instance, AMD's Radeon R9 Fury GPU first introduced in 2015.

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As the name implies, 2 .5D is an intermediate step towards 3D packaging, stacking and connecting multiple dies.

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We are now able to use a whole new dimension to achieve packaging efficiencies of over 100%.

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Connecting these dies may require something more heavy than your standard wire bonds, bringing forth new concepts like the through -silicon vias or TSVs.

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I am working on a future video on 3D integration and die stacking.

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So keep an eye out for that, If I ever finish it.

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The semiconductor packaging industry is truly a chaotic one.

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There are so many different technology trees growing concurrently with one another, each branch developing and splitting for a certain significant need.

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New technologies are built on top of those addressing particular niche applications,

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and then suddenly before you know it you have no idea why this new thing, which you saw fail a long time ago,

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is now such a big deal all over again.

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In the semiconductor packaging world, ideas are created and then vanish off the mainline, only to return to the forefront when their time is right.

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Expect more deep dives into semiconductor packaging in the near future as we familiarize ourselves with this new world.

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本课的词汇与口语要点

这节口语课以视频“A Brief History of Semiconductor Packaging”为素材。视频中反复出现的词有：package, packaging, board, lead, die。这段视频共有 215 个句子、2807 个单词可供跟读。讲话部分时长为 18:22。说话人语速自然，每分钟约 153 个词，接近日常对话。只有 73% 的单词属于英语最常用的 3,000 词，词汇难度较高。

视频中的重点词汇

视频中 15 个值得学习的单词，附发音和释义：

单词	发音	释义
package 名词	/ˈpæk.ɪd͡ʒ/	包裹, 包
mount 动词	/maʊnt/	騎 /骑
chip 名词	/t͡ʃɪp/	筹码
semiconductor 名词	/ˌsɛmikənˈdʌktə/	半導體 /半导体
wire 名词	/ˈwaɪɚ/	線 /线, 鐵絲 /铁丝
grid 名词	/ɡɹɪd/	網格 /网格, 格子
ceramic 名词	/səˈɹæmɪk/	陶瓷
integration 名词	/ˌɪn.tɪˈɡɹeɪ.ʃən/	融合, 統合 /统合
electronics 名词	/ɪˌlɛkˈtɹɑ.nɪks/	電子學 /电子学
silicon 名词	/ˈsɪləˌkɑn/	硅, 矽
refer 动词	/ɹɪˈfɜː/	談到 /谈到
connect 动词	/kəˈnɛkt/	連接 /连接
pin 名词	/pɪn/	別針 /别针
outline 名词	/ˈaʊtlaɪn/	輪廓 /轮廓
attach 动词	/əˈtæt͡ʃ/	附上, 附

视频中出现的短语动词

单词	释义
break down 动词	壞了 /坏了, 出故障
end up 动词	到达
slow down 动词	減速 /减速, 放慢
take over 动词	接管, 接手

视频中的语法

说话人最常用的结构，并附上视频中的原话：

结构	视频中的用法
被动语态 be + 过去分词 — 强调发生了什么，而不是谁做的	be connected · been chopped · are called
现在完成时 have/has + 过去分词 — 过去发生但与现在仍有关联的事	have taken · have stayed · have seen
定语从句 who / which + 从句 — 补充说明人或事物	world, which is · anymore, which means · life, which is

需要注意的发音

说话人用了 9 次缩略和弱读形式，例如 couldn't, don't, aren't。请按听到的简短形式来说。

“th” 音: underneath /ˌʌndɚˈniθ/, thin /ˈθɪn/, furthermore /ˈfɜː(ɹ).ðə(ɹ)ˌmɔː(ɹ)/, theoretical /ˌθi.əˈɹɛt.ɪ.kəl/
“sh” 和 “zh” 音: integration /ˌɪn.tɪˈɡɹeɪ.ʃən/, enclosure /ɛnˈkloʊʒəɹ/, evolution /ˌiːvəˈluːʃ(ə)n/, efficiency /ɪˈfɪʃ.ən.si/, ratio /ˈɹeɪ.ʃoʊ/
长单词——注意重音位置: semiconductor /ˌsɛmikənˈdʌktə/, integration /ˌɪn.tɪˈɡɹeɪ.ʃən/, electronics /ɪˌlɛkˈtɹɑ.nɪks/, electrical /ɪˈlɛktɹɪkəl/, manufacturer /ˌmænjʊˈfæktʃəɹə/

中文母语者容易读错的音：

/v/ — 不要读成 /w/，上齿轻触下唇: invent /ɪnˈvɛnt/, revive /ɹɪˈvaɪ̯v/, inventor /ɪnˈvɛntɚ/, evolution /ˌiːvəˈluːʃ(ə)n/, innovation /ˌɪn.əˈveɪ.ʃən/
词尾辅音 — 要读清楚，后面不要加元音: package /ˈpæk.ɪd͡ʒ/, mount /maʊnt/, chip /t͡ʃɪp/, circuit /ˈsɝ.kɪt/, quad /kwɑd/
/r/ 和 /l/ 的区别: electronics /ɪˌlɛkˈtɹɑ.nɪks/, enclosure /ɛnˈkloʊʒəɹ/, electrical /ɪˈlɛktɹɪkəl/, laboratory /ˈlæb(ə)ɹəˌtɔɹi/, ultra /ˈʌltɹə/

如何用这段视频练习

先完整听一遍视频，不要开口，记下不认识的单词。
先用 0.75 倍速逐句跟读，熟练之后再回到正常速度。
录下自己的声音并与原声对比，特别注意 package, mount, chip 这类单词。

什么是跟读法？

跟读法 (Shadowing) 是一种有科学依据的语言学习技巧，最初开发用于专业口译员的培训，并由多语言者Alexander Arguelles博士普及。这个方法简单而强大：您在听英语母语原声的同时立即大声重复——就像是一个延迟1-2秒紧跟说话者的影子。与被动听力或语法练习不同，跟读法强迫您的大脑和口腔肌肉同时处理并模仿真实的讲话模式。研究表明它能显着提高发音准确性，语调，节奏，连读，听力理解和口语流利度——使其成为雅思口语备考和真实英语交流最有效的方法之一。

影子跟读法: 阅读完整分步指南 →

跟读练习: A Brief History of Semiconductor Packaging - 通过视频学习英语口语

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