跟读练习: Making RAM at Home - 通过YouTube学习英语口语
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RAM prices have been insane.
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RAM prices have been insane.
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Driven by the rise in AI, it is causing massive disruption to the GPU, cell phone, PC markets, and more.
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And a key reason it's been so bad is that you have just three companies,
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Micron, Samsung, and SK Hynix, controlling the industry.
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Where new supply is not something that can appear overnight, building new fabs can take billions of dollars and years of work.
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So rather than wait around, I turned a shed in my backyard into a class 100 cleanroom and build my own semiconductor fabrication tools from scratch.
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Now the question is, can I actually make my own RAM?
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To start, how does RAM actually work?
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If we take a look and we zoomed in to one of the chips on a sticker RAM,
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where we would find our tens of thousands of rows and columns that make up an array,
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where each intersection has a transistor and a charge storage capacitor.
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The transistor acts as a switch, while the capacitor acts as a battery.
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When I turn on the transistor, it switches on the current and charges up the capacitor, storing one bit of information.
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I can then turn it off and hold the charge there.
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If I want to then read the data, I switch on the transistor again and the charge now flows backwards out so it can be detected.
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Though since that drains the capacitor, we have to refresh it and charge it back up periodically.
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But to build anything, we first need a design.
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I came up with a simple layout to have a 5x4 array that I could later stitch together,
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where each intersection has a transistor and a capacitor.
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I'm aiming for a small transistor, a gate length a bit less than 1 micron when finalized.
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Each color here in this figure represents a different layer, like a different floor in a house, as these devices are made layer by layer by layer,
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kind of like a sandwich.
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Silicone is the starting material for making RAM.
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Here I take a whole wafer and cleave it down to smaller workable chips.
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With a diamond scribe, silicon nicely cleaves along certain crystal planes.
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Kind of like a box with a bunch of 90 degree angles.
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Now after cleaving, there may be some debris on the wafer,
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so I use a solvent cleaning process with acetone and isopropanol alcohol.
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This is meant to remove some of the particles off of
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the surface as well as being able to dissolve any organics that may exist there.
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It doesn't have to be perfect
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because later on on our next step what we're going to
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do is we're going to convert the surface from silicon to glass anyways.
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The silicon chips are next loaded up into a furnace and heated to 1,100 degrees Celsius or 2,000 degrees Fahrenheit.
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We're talking volcanic lava temperatures.
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And this is in order to rust a silicon,
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effectively growing 3,300 angstroms of oxide or glass on the surface in order to mask and protect it,
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giving it this nice lime green color.
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With a layer of glass now on our silicon chips, it can be a little tricky in order to coat different materials.
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So I first apply lift off resist.
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I coat that onto the surface.
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Now this is normally meant, hence the name, for lifting off metal layers.
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But I find it actually works fantastic as an adhesion layer.
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This is then baked at 170 degrees Celsius for five minutes.
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Now, photo resist, or photosensitive patternable film, can be easily spin coated and spun onto this adhesion layer.
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After coating, it's baked at 100 degrees Celsius for two minutes to remove some of the excess solvent.
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The photoresist uniformly forms a thin film of a silicon chips, which is a little bit thicker than one micron.
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Photoresist acts as a patentable masking layer.
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UV light is used in combination with a mask, where the mask only allows light to pass through designed openings and shine onto the photoresist, exposing it.
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The UV light generates a photo acid, which when you take the sample and put it in a developer solution which is basic,
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the acid and base neutralize each other, generating a salt which is dissolved away.
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Basically, wherever you shine light, photoresist is now removed.
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So you have photo resist everywhere except for where the UV light illuminated.
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We use our first level from our design where the mask blocks light everywhere except for where our design is.
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The microscope stepper system has objectives which then shrink this pattern down right to where our sample is going to be.
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The higher magnifications further shrink that design down until you can't make out the sub-micron features.
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We can see the design through the eyepieces and the camera, where custom software controls the focus and exposure.
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The areas exposed to UV light are developed with our robot friend for better uniformity,
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and ultimately removed, forming our patterned photoresist.
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Using the photoresist layer as a mask, the patterned areas are dry-etched,
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where we selectively remove that glass layer to get back down to the silicon surface.
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With the edging step complete, we no longer need the photoresist mask.
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So the photoresist is stripped in heated DMSO.
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Weird enough, people actually take this as a form of medication.
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But the semiconductor industry actually uses it as a strong solvent to remove photoresistant LOR.
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So this leaves us with windows now in our 3,300 angstroms of oxide or glass on silicon.
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We did this as the oxide itself acts now as a high temperature mask for our next step,
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which it involves forming the source and drain of our transistor.
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You can think of the source and drain as effectively the input and output terminals for our switch,
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the gate or switchy part will be later formed in the middle.
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We accomplish this by introducing dopants into the material in these windows here
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and that makes these regions highly conductive input outputs and this is by adding phosphorus into the silicon.
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So how in the world do we do that?
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How do we add phosphorus into the silicon?
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So there are a number of commercial products that do this.
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The industry also makes use of ion implantation, but that is ridiculously expensive, and it's too large of a footprint for a shed.
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So Projects in Flight actually made a fantastic video on this, making phosphorus-doped spin-on glass as opposed to buying it.
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I tested the solution first on a test piece, where the initial wafer is so resistive that a multimeter can't easily detect continuity
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but on a treated sample it is now highly conductive
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and uh kind of working towards degeneratively dope a very high level of doping
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which is perfect repeating this on our main chips we can coat the phosphorus dope spin on glass
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and then we can proceed to bake it where the temperature
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is ramped up slowly in order to drive out all the solvents but not cause undue stress or cracking.
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It looks good, however there are a handful of glass precipitates that can form during synthesis.
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While this shouldn't be an issue and it's mostly cosmetic, next time the better thing to do is to filter it in order to remove any glass precipitates.
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I made a calculator in order to model effectively the depth of our phosphorus doping profile.
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what's that going to look like?
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Because what we want is that we want effectively a more shallow profile for what we're aiming for.
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And to get
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that, what we're going to do is we're first going to
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anneal with the phosphorus dope spin on glass at 1100 degrees Celsius for five minutes.
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Strip of the spin on glass in hydrofluoric acid and then do a drive-in anneal at 1000 degrees Celsius for 10 minutes.
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With the source and drain, the input output electrical terminals for our switch,
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for our transistor, we can now focus on the switch aspect itself, the gate region of our transistor.
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LOR, lift-off resist, or makeshift adhesion layer, is then coated because we still have glass on the surface.
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Followed by our photo resist layer, again that patternable layer.
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We coat both of them again.
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With these layers down, we can then pattern and form the channel region of our transistor.
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To do that, we need this layer to be aligned between our previously formed source and drain regions.
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While we're at it, we're also going to align and expose the area that will form our charge storage capacitor,
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which is right above our transistors.
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After development, an HFH is used to remove the middle oxide between the source and drain,
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as well as next to the transistor for our charge storage capacitor.
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This is because the oxide is too thick there and we want a custom oxide thickness for our gate and capacitor.
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The channel region of our transistor, the thing that does our switching, is the most critical region.
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As such, I perform a clean known as a piranha clean
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which will viciously attack any organics and most metals on the surface.
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They call it piranha as it can eat material
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and flush just like a piranha fish in the Amazon going after a chicken leg.
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The samples are loaded back into the furnace to grow the gate and capacitor oxides.
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We want this thinner so we have more capacitance and better gate control.
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So we're going to grow at a lower temperature of only 950 degrees Celsius.
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And if we put it in there for 38 minutes, we get 200 angstroms, or 20 nanometers, of oxide.
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This is what the structure looks like now, where we have our gate and capacitor oxides grown again at 20 nanometers,
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where we still have thicker oxide outside of the device.
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But because everything is covered in oxide, what we need to do is we need to punch some holes selectively through
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that oxide in order to later form electrical contacts to the device.
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More LOR and photoresist are coated and baked, and then the contact cut mask is carefully aligned and exposed,
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where after development, we're left with some small openings in the LOR and photoresist.
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HF or hydrofluoric acid is again utilized where
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that can go into the photoresist and LOR openings in order to remove any glass on the silicon surface,
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thereby forming a nice pathway for electrical connection.
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For the final level in our device, we need to deposit metal to form the gate of our transistor electrical contacts,
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as well as the capacitor itself.
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To do this, LOR and photoresist are coated and baked, and then we can align and expose the final mass level.
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Though this level is a bit different than our previous levels, where our previous levels were all focused on removing material.
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With this, what we're doing now is that we're using the photoresist openings that we have
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in order to treat them as a stencil combined with a metal deposition process.
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A good analogy for this is that if we wanted to paint something, such as a handicap sign over here, what we might do is that we might use a stencil,
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in this case a metal stencil, where we could deposit material by spray painting,
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for instance, and then when we remove our stencil, we're just left with the design where we want.
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Well, that's effectively what we're doing here at the nanoscale with the pattern that we've created.
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But instead of spray painting, what we're actually doing is that we're effectively spraying the surface with metal atoms, in this case, aluminum here,
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where the sample is loaded up into my sputter system, where we have argon that hits the metal target,
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and then the metal atoms fall off and are effectively sprayed, so to speak, onto our sample.
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So as you can see, the metal has been uniformly coated over the sample, except where there was some capped on tape at the edges there.
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So how do we effectively remove our stencil?
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How do we remove the photoresist layers here?
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Well we can stick that in once again DMSO and heat that up.
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It's always cool to see where we can start to see the metal buckle
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and then eventually start to peel off of the surface.
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If I apply a little bit of agitation there we can aid in its removal just leaving the pattern
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that we want looking at it under the microscope post liftoff process what we can see is
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that we can see our complete structure now we have the transistors the capacitors all the connections
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that we need in order to have our DRAM array
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if we were to look at a cross section this is the structure
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that we have
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and then this is how it matches up to our earlier little cartoon where we can have current flow
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and be controlled by the transistor by our switch where it
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can charge up our charge storage capacitor in order to hold a bit of data now as
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if the shed wasn't enough inside in my living room i held a whole suite of test equipment
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so i got my little lab assistant here
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and i'm going to fire up one of these semiconductor parameter analyzes in order to look at the results.
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Because these devices are of course at the nano scale, you can't just attach regular wires easily to them.
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So for testing purposes, what I have set up here is
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that I have a number of these micro manipulators with some
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incredibly fine probe tips in order to feed electrical current
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and voltage into the device and then be able to read that out.
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When testing the transistor, our switch, I get the following results.
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Each line represents a different gate voltage, where I can have different levels of current, or nearly no current depending on the gate voltage I apply.
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This acts like our switch, or more specifically, it can act like one of those dimmer switches, where as I turn and adjust,
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I can tune the level of output power.
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But for RAM, we can just settle for basic on-off operation.
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Normally, though, in a transistor, current saturates.
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These lines stay flat.
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It doesn't shoot up at higher voltages.
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What we're seeing is a short channel effect known as punch-through.
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So because the source and drain are less than one micron away from each other,
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as we increase the voltage that we apply, they can effectively merge.
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and this leads to an increase in current and a loss of gate control.
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Now this is fine as long as we operate our devices at lower voltages, but it certainly shows the challenges of scaling.
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So let's look at the other half of the equation, the charge storage capacitor that we have.
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So here I have a CV plotter, which is a very sensitive instrument for reading up the capacitance as I
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scan through and then vary the voltage across the capacitor
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because the capacitor will have a minimum and a maximum capacitance of course in
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which it can store and that maximum capacitance I recorded as 12.3 picofarads
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which is pretty close to the perfect ideal theoretical of a little bit less than 15 picofarads
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which I had designed for looking at them together now as one individual DRAM cell,
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the transistor can very rapidly and quickly charge up our charge storage capacitor to 3 volts within a couple hundred nanoseconds,
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which is great, and then it'll hold that voltage on there
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but it'll slightly bleed off over time where we can only hold
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that charge on there for a little bit over two milliseconds before it's completely done for.
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We need to charge it back up if not sooner.
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Commercial DRAM can hold its charge for greater than 64 milliseconds, so in this design it needs to be refreshed at a higher frequency.
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Okay, this is awesome.
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First time ever RAM has been made at home, but while you can store data on it, you can't run DOOM on it quite yet.
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This is just a few cells to prove it can work.
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The next step is to take these cells, to stitch them together in order to make a much larger array.
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Then we can hook it up to a PC.
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Stay tuned.
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Massive thanks to everyone subscribed on Patreon who helped support this work.
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Link below.
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背景与背景
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日常沟通的五个关键短语
- 半导体制造 - 了解这一过程可以帮助你在科技相关的谈话中游刃有余。
- 洁净室 - 这是专业术语，适用于谈论高科技环境和设备。
- 硅片清理 - 涉及一个关键的工艺流程，能够展示你对技术细节的掌握。
- 光刻胶 - 这一技术术语会在科技术语交流中频繁出现。
- 温度控制 - 在讨论制造过程中常常提到的重要参数。
逐步影子跟读指南
在观看此视频时，你可以通过英语影子跟读方法来提高你的语言能力。首先，注意讲者的发音和语调。可以按照以下步骤进行练习：
- 选择一段你感兴趣的内容，最好是视频开头，以便于快速抓住主题。
- 首先听一遍，理解大意。然后暂停，重复每一句话，尝试模仿讲者的发音。特别注意技术性词汇的正确发音。
- 利用视频中的术语，进行英语口语练习。尝试用这些词汇进行造句，例如：“我在家里尝试制作半导体。”
- 用shadow speak的方法，逐句跟随讲者的节奏，练习到能够流利为止。在这个过程中，努力提高发音和语调的准确性。
- 最后，可以与学习伙伴交流你所学到的知识，并采取雅思口语练习中所使用的技术进行互动。
通过这些方法，你不仅能提升提高英语发音的能力，还能在高科技和工程领域内提升自己的专业英语水平，助力未来的职业发展。
什么是跟读法？
跟读法 (Shadowing) 是一种有科学依据的语言学习技巧，最初开发用于专业口译员的培训，并由多语言者Alexander Arguelles博士普及。这个方法简单而强大：您在听英语母语原声的同时立即大声重复——就像是一个延迟1-2秒紧跟说话者的影子。与被动听力或语法练习不同，跟读法强迫您的大脑和口腔肌肉同时处理并模仿真实的讲话模式。研究表明它能显着提高发音准确性，语调，节奏，连读，听力理解和口语流利度——使其成为雅思口语备考和真实英语交流最有效的方法之一。