शैडोइंग अभ्यास: Making RAM at Home - वीडियो के साथ अंग्रेजी बोलना सीखें
अभ्यास मोड चुनें
हर मोड पूरी स्क्रीन का अभ्यास कक्ष खोलता है।
192 वाक्य
यदि वाक्य बहुत छोटे या लंबे हों, तो समायोजित करने के लिए Edit पर क्लिक करें।
1
RAM prices have been insane.
2
Driven by the rise in AI, it is causing massive disruption to the GPU, cell phone, PC markets, and more.
3
And a key reason it's been so bad is that you have just three companies,
4
Micron, Samsung, and SK Hynix, controlling the industry.
5
Where new supply is not something that can appear overnight, building new fabs can take billions of dollars and years of work.
6
So rather than wait around, I turned a shed in my backyard into a class 100 cleanroom and build my own semiconductor fabrication tools from scratch.
7
Now the question is, can I actually make my own RAM?
8
To start, how does RAM actually work?
9
If we take a look and we zoomed in to one of the chips on a sticker RAM,
10
where we would find our tens of thousands of rows and columns that make up an array,
11
where each intersection has a transistor and a charge storage capacitor.
12
The transistor acts as a switch, while the capacitor acts as a battery.
13
When I turn on the transistor, it switches on the current and charges up the capacitor, storing one bit of information.
14
I can then turn it off and hold the charge there.
15
If I want to then read the data, I switch on the transistor again and the charge now flows backwards out so it can be detected.
16
Though since that drains the capacitor, we have to refresh it and charge it back up periodically.
17
But to build anything, we first need a design.
18
I came up with a simple layout to have a 5x4 array that I could later stitch together,
19
where each intersection has a transistor and a capacitor.
20
I'm aiming for a small transistor, a gate length a bit less than 1 micron when finalized.
21
Each color here in this figure represents a different layer, like a different floor in a house, as these devices are made layer by layer by layer,
22
kind of like a sandwich.
23
Silicone is the starting material for making RAM.
24
Here I take a whole wafer and cleave it down to smaller workable chips.
25
With a diamond scribe, silicon nicely cleaves along certain crystal planes.
26
Kind of like a box with a bunch of 90 degree angles.
27
Now after cleaving, there may be some debris on the wafer,
28
so I use a solvent cleaning process with acetone and isopropanol alcohol.
29
This is meant to remove some of the particles off of
30
the surface as well as being able to dissolve any organics that may exist there.
31
It doesn't have to be perfect
32
because later on on our next step what we're going to
33
do is we're going to convert the surface from silicon to glass anyways.
34
The silicon chips are next loaded up into a furnace and heated to 1,100 degrees Celsius or 2,000 degrees Fahrenheit.
35
We're talking volcanic lava temperatures.
36
And this is in order to rust a silicon,
37
effectively growing 3,300 angstroms of oxide or glass on the surface in order to mask and protect it,
38
giving it this nice lime green color.
39
With a layer of glass now on our silicon chips, it can be a little tricky in order to coat different materials.
40
So I first apply lift off resist.
41
I coat that onto the surface.
42
Now this is normally meant, hence the name, for lifting off metal layers.
43
But I find it actually works fantastic as an adhesion layer.
44
This is then baked at 170 degrees Celsius for five minutes.
45
Now, photo resist, or photosensitive patternable film, can be easily spin coated and spun onto this adhesion layer.
46
After coating, it's baked at 100 degrees Celsius for two minutes to remove some of the excess solvent.
47
The photoresist uniformly forms a thin film of a silicon chips, which is a little bit thicker than one micron.
48
Photoresist acts as a patentable masking layer.
49
UV light is used in combination with a mask, where the mask only allows light to pass through designed openings and shine onto the photoresist, exposing it.
50
The UV light generates a photo acid, which when you take the sample and put it in a developer solution which is basic,
51
the acid and base neutralize each other, generating a salt which is dissolved away.
52
Basically, wherever you shine light, photoresist is now removed.
53
So you have photo resist everywhere except for where the UV light illuminated.
54
We use our first level from our design where the mask blocks light everywhere except for where our design is.
55
The microscope stepper system has objectives which then shrink this pattern down right to where our sample is going to be.
56
The higher magnifications further shrink that design down until you can't make out the sub-micron features.
57
We can see the design through the eyepieces and the camera, where custom software controls the focus and exposure.
58
The areas exposed to UV light are developed with our robot friend for better uniformity,
59
and ultimately removed, forming our patterned photoresist.
60
Using the photoresist layer as a mask, the patterned areas are dry-etched,
61
where we selectively remove that glass layer to get back down to the silicon surface.
62
With the edging step complete, we no longer need the photoresist mask.
63
So the photoresist is stripped in heated DMSO.
64
Weird enough, people actually take this as a form of medication.
65
But the semiconductor industry actually uses it as a strong solvent to remove photoresistant LOR.
66
So this leaves us with windows now in our 3,300 angstroms of oxide or glass on silicon.
67
We did this as the oxide itself acts now as a high temperature mask for our next step,
68
which it involves forming the source and drain of our transistor.
69
You can think of the source and drain as effectively the input and output terminals for our switch,
70
the gate or switchy part will be later formed in the middle.
71
We accomplish this by introducing dopants into the material in these windows here
72
and that makes these regions highly conductive input outputs and this is by adding phosphorus into the silicon.
73
So how in the world do we do that?
74
How do we add phosphorus into the silicon?
75
So there are a number of commercial products that do this.
76
The industry also makes use of ion implantation, but that is ridiculously expensive, and it's too large of a footprint for a shed.
77
So Projects in Flight actually made a fantastic video on this, making phosphorus-doped spin-on glass as opposed to buying it.
78
I tested the solution first on a test piece, where the initial wafer is so resistive that a multimeter can't easily detect continuity
79
but on a treated sample it is now highly conductive
80
and uh kind of working towards degeneratively dope a very high level of doping
81
which is perfect repeating this on our main chips we can coat the phosphorus dope spin on glass
82
and then we can proceed to bake it where the temperature
83
is ramped up slowly in order to drive out all the solvents but not cause undue stress or cracking.
84
It looks good, however there are a handful of glass precipitates that can form during synthesis.
85
While this shouldn't be an issue and it's mostly cosmetic, next time the better thing to do is to filter it in order to remove any glass precipitates.
86
I made a calculator in order to model effectively the depth of our phosphorus doping profile.
87
what's that going to look like?
88
Because what we want is that we want effectively a more shallow profile for what we're aiming for.
89
And to get
90
that, what we're going to do is we're first going to
91
anneal with the phosphorus dope spin on glass at 1100 degrees Celsius for five minutes.
92
Strip of the spin on glass in hydrofluoric acid and then do a drive-in anneal at 1000 degrees Celsius for 10 minutes.
93
With the source and drain, the input output electrical terminals for our switch,
94
for our transistor, we can now focus on the switch aspect itself, the gate region of our transistor.
95
LOR, lift-off resist, or makeshift adhesion layer, is then coated because we still have glass on the surface.
96
Followed by our photo resist layer, again that patternable layer.
97
We coat both of them again.
98
With these layers down, we can then pattern and form the channel region of our transistor.
99
To do that, we need this layer to be aligned between our previously formed source and drain regions.
100
While we're at it, we're also going to align and expose the area that will form our charge storage capacitor,
101
which is right above our transistors.
102
After development, an HFH is used to remove the middle oxide between the source and drain,
103
as well as next to the transistor for our charge storage capacitor.
104
This is because the oxide is too thick there and we want a custom oxide thickness for our gate and capacitor.
105
The channel region of our transistor, the thing that does our switching, is the most critical region.
106
As such, I perform a clean known as a piranha clean
107
which will viciously attack any organics and most metals on the surface.
108
They call it piranha as it can eat material
109
and flush just like a piranha fish in the Amazon going after a chicken leg.
110
The samples are loaded back into the furnace to grow the gate and capacitor oxides.
111
We want this thinner so we have more capacitance and better gate control.
112
So we're going to grow at a lower temperature of only 950 degrees Celsius.
113
And if we put it in there for 38 minutes, we get 200 angstroms, or 20 nanometers, of oxide.
114
This is what the structure looks like now, where we have our gate and capacitor oxides grown again at 20 nanometers,
115
where we still have thicker oxide outside of the device.
116
But because everything is covered in oxide, what we need to do is we need to punch some holes selectively through
117
that oxide in order to later form electrical contacts to the device.
118
More LOR and photoresist are coated and baked, and then the contact cut mask is carefully aligned and exposed,
119
where after development, we're left with some small openings in the LOR and photoresist.
120
HF or hydrofluoric acid is again utilized where
121
that can go into the photoresist and LOR openings in order to remove any glass on the silicon surface,
122
thereby forming a nice pathway for electrical connection.
123
For the final level in our device, we need to deposit metal to form the gate of our transistor electrical contacts,
124
as well as the capacitor itself.
125
To do this, LOR and photoresist are coated and baked, and then we can align and expose the final mass level.
126
Though this level is a bit different than our previous levels, where our previous levels were all focused on removing material.
127
With this, what we're doing now is that we're using the photoresist openings that we have
128
in order to treat them as a stencil combined with a metal deposition process.
129
A good analogy for this is that if we wanted to paint something, such as a handicap sign over here, what we might do is that we might use a stencil,
130
in this case a metal stencil, where we could deposit material by spray painting,
131
for instance, and then when we remove our stencil, we're just left with the design where we want.
132
Well, that's effectively what we're doing here at the nanoscale with the pattern that we've created.
133
But instead of spray painting, what we're actually doing is that we're effectively spraying the surface with metal atoms, in this case, aluminum here,
134
where the sample is loaded up into my sputter system, where we have argon that hits the metal target,
135
and then the metal atoms fall off and are effectively sprayed, so to speak, onto our sample.
136
So as you can see, the metal has been uniformly coated over the sample, except where there was some capped on tape at the edges there.
137
So how do we effectively remove our stencil?
138
How do we remove the photoresist layers here?
139
Well we can stick that in once again DMSO and heat that up.
140
It's always cool to see where we can start to see the metal buckle
141
and then eventually start to peel off of the surface.
142
If I apply a little bit of agitation there we can aid in its removal just leaving the pattern
143
that we want looking at it under the microscope post liftoff process what we can see is
144
that we can see our complete structure now we have the transistors the capacitors all the connections
145
that we need in order to have our DRAM array
146
if we were to look at a cross section this is the structure
147
that we have
148
and then this is how it matches up to our earlier little cartoon where we can have current flow
149
and be controlled by the transistor by our switch where it
150
can charge up our charge storage capacitor in order to hold a bit of data now as
151
if the shed wasn't enough inside in my living room i held a whole suite of test equipment
152
so i got my little lab assistant here
153
and i'm going to fire up one of these semiconductor parameter analyzes in order to look at the results.
154
Because these devices are of course at the nano scale, you can't just attach regular wires easily to them.
155
So for testing purposes, what I have set up here is
156
that I have a number of these micro manipulators with some
157
incredibly fine probe tips in order to feed electrical current
158
and voltage into the device and then be able to read that out.
159
When testing the transistor, our switch, I get the following results.
160
Each line represents a different gate voltage, where I can have different levels of current, or nearly no current depending on the gate voltage I apply.
161
This acts like our switch, or more specifically, it can act like one of those dimmer switches, where as I turn and adjust,
162
I can tune the level of output power.
163
But for RAM, we can just settle for basic on-off operation.
164
Normally, though, in a transistor, current saturates.
165
These lines stay flat.
166
It doesn't shoot up at higher voltages.
167
What we're seeing is a short channel effect known as punch-through.
168
So because the source and drain are less than one micron away from each other,
169
as we increase the voltage that we apply, they can effectively merge.
170
and this leads to an increase in current and a loss of gate control.
171
Now this is fine as long as we operate our devices at lower voltages, but it certainly shows the challenges of scaling.
172
So let's look at the other half of the equation, the charge storage capacitor that we have.
173
So here I have a CV plotter, which is a very sensitive instrument for reading up the capacitance as I
174
scan through and then vary the voltage across the capacitor
175
because the capacitor will have a minimum and a maximum capacitance of course in
176
which it can store and that maximum capacitance I recorded as 12.3 picofarads
177
which is pretty close to the perfect ideal theoretical of a little bit less than 15 picofarads
178
which I had designed for looking at them together now as one individual DRAM cell,
179
the transistor can very rapidly and quickly charge up our charge storage capacitor to 3 volts within a couple hundred nanoseconds,
180
which is great, and then it'll hold that voltage on there
181
but it'll slightly bleed off over time where we can only hold
182
that charge on there for a little bit over two milliseconds before it's completely done for.
183
We need to charge it back up if not sooner.
184
Commercial DRAM can hold its charge for greater than 64 milliseconds, so in this design it needs to be refreshed at a higher frequency.
185
Okay, this is awesome.
186
First time ever RAM has been made at home, but while you can store data on it, you can't run DOOM on it quite yet.
187
This is just a few cells to prove it can work.
188
The next step is to take these cells, to stitch them together in order to make a much larger array.
189
Then we can hook it up to a PC.
190
Stay tuned.
191
Massive thanks to everyone subscribed on Patreon who helped support this work.
192
Link below.
ऐप डाउनलोड करें
धाराप्रवाह बोलने के लिए ज़रूरी सब कुछ
AI उच्चारण स्कोरहर वाक्य का स्कोर
IPA अभ्यासहर ध्वनि में महारत
शब्दावलीअपना शब्द भंडार बनाएँ
शब्द गेमखेलते हुए सीखें
FOR YOU
अनुशंसित वीडियो
C19
265 वाक्य
How are Microchips Made? 🖥️🛠️ CPU Manufacturing Process Steps
Business EnglishUniversity StudentsWorking Adults
C12
151 वाक्य
Wrote My Own Memory Allocator (and ran DOOM with It)
Business EnglishUniversity StudentsWorking Adults
C11
124 वाक्य
How to Make Anything - Learn to Think Like an Engineer
Business EnglishUniversity StudentsWorking Adults
C13
131 वाक्य
Understanding BGA Pads: Solder Mask Defined vs Non-Defined
Business EnglishUniversity StudentsWorking Adults
C11
462 वाक्य
Expensive RTX 5090 for LLMs? NO. Use This Instead. (Tesla V100 SXM2 + Z8 G4, #RACERRRZ)
Daily ConversationUniversity StudentsWorking Adults
C13
51 वाक्य
How to do ACTIVE RECALL Effectively? (4 Techniques worked for me)
Business EnglishUniversity StudentsWorking Adults
C12
306 वाक्य
Deep Dive: Investigating Thermal Cycling Failures Cracked MSOP Solder Joints
Business EnglishUniversity StudentsWorking Adults
C12
133 वाक्य
Carbon Fiber - The Material Of The Future?
Business EnglishUniversity StudentsWorking Adults
C13
101 वाक्य
How Does a URL Shortener Work?
Business EnglishInterview EnglishUniversity Students
C14
413 वाक्य
Exposing The Flaw In Our Phone System
Business EnglishUniversity StudentsWorking Adults
C11
65 वाक्य
How do microSD Cards Store 2 TB in such a TINY space?
Daily ConversationUniversity StudentsWorking Adults
B24
31 वाक्य
What happens to old electronic devices when you upgrade?
Business EnglishDaily ConversationUniversity Students
इस पाठ के बारे में
इस पाठ में, आप यूट्यूब वीडियो से बातचीत को सुनते हुए अंग्रेजी बोलने का अभ्यास करेंगे। वीडियो में प्रस्तुत जानकारी का उद्देश्य RAM बनाने की प्रक्रिया को सरल तरीके से समझाना है। आप तकनीकी शब्दावली, वाक्य संरचना और उच्चारण से संबंधित कौशल विकसित करेंगे। इस अभ्यास के माध्यम से आप अंग्रेजी उच्चारण में सुधार कर सकते हैं और प्रभावी ढंग से संवाद करना सीखेंगे।
मुख्य शब्दावली और वाक्यांश
- RAM: याद रखने की एक तकनीकी इकाई
- Transistor: एक इलेक्ट्रॉनिक स्विच
- Capacitor: चार्ज संग्रहित करने का उपकरण
- Silicon: एक प्रमुख अर्धचालक सामग्री
- Oxide: सिलिकॉन पर रखा जाने वाला सुरक्षात्मक परत
- Photoresist: प्रकाश के प्रति संवेदनशील परत
- Lift-off resist: धातु की परतों को हटाने के लिए उपयोग किया जाने वाला सामग्री
- Furnace: उच्च तापमान में सामग्री को गर्म करने की इकाई
अभ्यास युक्तियाँ
इस वीडियो की बातचीत के साथ अंग्रेजी बोलने का अभ्यास करते समय, निम्नलिखित सुझावों का पालन करें:
- वीडियो को एक बार सुनें और उस संदर्भ को समझें जिससे बातचीत की जा रही है।
- फिर से सुनें और shadow speech तकनीक का उपयोग करें, यानी शीर्षक वाले शब्दों और वाक्यांशों को धीरे-धीरे दोहराएं।
- वीडियो की गति के साथ तालमेल बिठाने की कोशिश करें; यह आपको अंग्रेजी उच्चारण में सुधार करने में मदद करेगा।
- अवधारणाओं को समझने के लिए नोट्स बनाएं और उन पर अपने शब्दों में विचार करें।
- प्रत्येक सेक्शन के बाद रुकें और जो कुछ आपने सुना है उसका पुनरावृत्ति करें, यह आपके shadowspeak कौशल को विकसित करेगा।
इस प्रकार, आप यूट्यूब से अंग्रेजी सीखने और अपने संवाद कौशल को बढ़ाने में सक्षम होंगे।
इस वीडियो का व्याकरण
वक्ता जिन संरचनाओं का सबसे अधिक प्रयोग करता है, वीडियो के असली शब्दों के साथ:
| संरचना | वीडियो में |
|---|---|
| Passive voice be + past participle — ज़ोर इस पर कि क्या होता है, न कि कौन करता है | can be detected · are made · is meant |
| Present perfect have/has + past participle — बीता हुआ काम जिसका असर अभी भी है | have been · it's been · we've created |
| Relative clauses who / which + उपवाक्य — व्यक्ति या वस्तु के बारे में अतिरिक्त जानकारी | chips, which is · solution which is · salt which is |
शैडोइंग तकनीक क्या है?
शैडोइंग (Shadowing) एक विज्ञान-समर्थित भाषा सीखने की तकनीक है जो मूल रूप से पेशेवर दुभाषिया प्रशिक्षण के लिए विकसित की गई थी। विधि सरल लेकिन शक्तिशाली है: आप मूल अंग्रेज़ी ऑडियो सुनते हैं और तुरंत इसे ज़ोर से दोहराते हैं — जैसे वक्ता की छाया 1-2 सेकंड की देरी से। शोध से पता चलता है कि यह उच्चारण सटीकता, स्वर, लय, जुड़ी हुई ध्वनियाँ, सुनने की समझ और बोलने की प्रवाहशीलता में काफ़ी सुधार करता है।