跟讀練習: Making RAM at Home - 通過影片學習英語口語

選擇練習模式

每種模式都會開啟全屏練習室。

192 句

如果句子過短或過長，請點選 Edit 進行調整。

RAM prices have been insane.

Driven by the rise in AI, it is causing massive disruption to the GPU, cell phone, PC markets, and more.

And a key reason it's been so bad is that you have just three companies,

Micron, Samsung, and SK Hynix, controlling the industry.

Where new supply is not something that can appear overnight, building new fabs can take billions of dollars and years of work.

So rather than wait around, I turned a shed in my backyard into a class 100 cleanroom and build my own semiconductor fabrication tools from scratch.

Now the question is, can I actually make my own RAM?

To start, how does RAM actually work?

If we take a look and we zoomed in to one of the chips on a sticker RAM,

where we would find our tens of thousands of rows and columns that make up an array,

where each intersection has a transistor and a charge storage capacitor.

The transistor acts as a switch, while the capacitor acts as a battery.

When I turn on the transistor, it switches on the current and charges up the capacitor, storing one bit of information.

I can then turn it off and hold the charge there.

If I want to then read the data, I switch on the transistor again and the charge now flows backwards out so it can be detected.

Though since that drains the capacitor, we have to refresh it and charge it back up periodically.

But to build anything, we first need a design.

I came up with a simple layout to have a 5x4 array that I could later stitch together,

where each intersection has a transistor and a capacitor.

I'm aiming for a small transistor, a gate length a bit less than 1 micron when finalized.

Each color here in this figure represents a different layer, like a different floor in a house, as these devices are made layer by layer by layer,

kind of like a sandwich.

Silicone is the starting material for making RAM.

Here I take a whole wafer and cleave it down to smaller workable chips.

With a diamond scribe, silicon nicely cleaves along certain crystal planes.

Kind of like a box with a bunch of 90 degree angles.

Now after cleaving, there may be some debris on the wafer,

so I use a solvent cleaning process with acetone and isopropanol alcohol.

This is meant to remove some of the particles off of

the surface as well as being able to dissolve any organics that may exist there.

It doesn't have to be perfect

because later on on our next step what we're going to

do is we're going to convert the surface from silicon to glass anyways.

The silicon chips are next loaded up into a furnace and heated to 1,100 degrees Celsius or 2,000 degrees Fahrenheit.

We're talking volcanic lava temperatures.

And this is in order to rust a silicon,

effectively growing 3,300 angstroms of oxide or glass on the surface in order to mask and protect it,

giving it this nice lime green color.

With a layer of glass now on our silicon chips, it can be a little tricky in order to coat different materials.

So I first apply lift off resist.

I coat that onto the surface.

Now this is normally meant, hence the name, for lifting off metal layers.

But I find it actually works fantastic as an adhesion layer.

This is then baked at 170 degrees Celsius for five minutes.

Now, photo resist, or photosensitive patternable film, can be easily spin coated and spun onto this adhesion layer.

After coating, it's baked at 100 degrees Celsius for two minutes to remove some of the excess solvent.

The photoresist uniformly forms a thin film of a silicon chips, which is a little bit thicker than one micron.

Photoresist acts as a patentable masking layer.

UV light is used in combination with a mask, where the mask only allows light to pass through designed openings and shine onto the photoresist, exposing it.

The UV light generates a photo acid, which when you take the sample and put it in a developer solution which is basic,

the acid and base neutralize each other, generating a salt which is dissolved away.

Basically, wherever you shine light, photoresist is now removed.

So you have photo resist everywhere except for where the UV light illuminated.

We use our first level from our design where the mask blocks light everywhere except for where our design is.

The microscope stepper system has objectives which then shrink this pattern down right to where our sample is going to be.

The higher magnifications further shrink that design down until you can't make out the sub-micron features.

We can see the design through the eyepieces and the camera, where custom software controls the focus and exposure.

The areas exposed to UV light are developed with our robot friend for better uniformity,

and ultimately removed, forming our patterned photoresist.

Using the photoresist layer as a mask, the patterned areas are dry-etched,

where we selectively remove that glass layer to get back down to the silicon surface.

With the edging step complete, we no longer need the photoresist mask.

So the photoresist is stripped in heated DMSO.

Weird enough, people actually take this as a form of medication.

But the semiconductor industry actually uses it as a strong solvent to remove photoresistant LOR.

So this leaves us with windows now in our 3,300 angstroms of oxide or glass on silicon.

We did this as the oxide itself acts now as a high temperature mask for our next step,

which it involves forming the source and drain of our transistor.

You can think of the source and drain as effectively the input and output terminals for our switch,

the gate or switchy part will be later formed in the middle.

We accomplish this by introducing dopants into the material in these windows here

and that makes these regions highly conductive input outputs and this is by adding phosphorus into the silicon.

So how in the world do we do that?

How do we add phosphorus into the silicon?

So there are a number of commercial products that do this.

The industry also makes use of ion implantation, but that is ridiculously expensive, and it's too large of a footprint for a shed.

So Projects in Flight actually made a fantastic video on this, making phosphorus-doped spin-on glass as opposed to buying it.

I tested the solution first on a test piece, where the initial wafer is so resistive that a multimeter can't easily detect continuity

but on a treated sample it is now highly conductive

and uh kind of working towards degeneratively dope a very high level of doping

which is perfect repeating this on our main chips we can coat the phosphorus dope spin on glass

and then we can proceed to bake it where the temperature

is ramped up slowly in order to drive out all the solvents but not cause undue stress or cracking.

It looks good, however there are a handful of glass precipitates that can form during synthesis.

While this shouldn't be an issue and it's mostly cosmetic, next time the better thing to do is to filter it in order to remove any glass precipitates.

I made a calculator in order to model effectively the depth of our phosphorus doping profile.

what's that going to look like?

Because what we want is that we want effectively a more shallow profile for what we're aiming for.

And to get

that, what we're going to do is we're first going to

anneal with the phosphorus dope spin on glass at 1100 degrees Celsius for five minutes.

Strip of the spin on glass in hydrofluoric acid and then do a drive-in anneal at 1000 degrees Celsius for 10 minutes.

With the source and drain, the input output electrical terminals for our switch,

for our transistor, we can now focus on the switch aspect itself, the gate region of our transistor.

LOR, lift-off resist, or makeshift adhesion layer, is then coated because we still have glass on the surface.

Followed by our photo resist layer, again that patternable layer.

We coat both of them again.

With these layers down, we can then pattern and form the channel region of our transistor.

To do that, we need this layer to be aligned between our previously formed source and drain regions.

100

While we're at it, we're also going to align and expose the area that will form our charge storage capacitor,

101

which is right above our transistors.

102

After development, an HFH is used to remove the middle oxide between the source and drain,

103

as well as next to the transistor for our charge storage capacitor.

104

This is because the oxide is too thick there and we want a custom oxide thickness for our gate and capacitor.

105

The channel region of our transistor, the thing that does our switching, is the most critical region.

106

As such, I perform a clean known as a piranha clean

107

which will viciously attack any organics and most metals on the surface.

108

They call it piranha as it can eat material

109

and flush just like a piranha fish in the Amazon going after a chicken leg.

110

The samples are loaded back into the furnace to grow the gate and capacitor oxides.

111

We want this thinner so we have more capacitance and better gate control.

112

So we're going to grow at a lower temperature of only 950 degrees Celsius.

113

And if we put it in there for 38 minutes, we get 200 angstroms, or 20 nanometers, of oxide.

114

This is what the structure looks like now, where we have our gate and capacitor oxides grown again at 20 nanometers,

115

where we still have thicker oxide outside of the device.

116

But because everything is covered in oxide, what we need to do is we need to punch some holes selectively through

117

that oxide in order to later form electrical contacts to the device.

118

More LOR and photoresist are coated and baked, and then the contact cut mask is carefully aligned and exposed,

119

where after development, we're left with some small openings in the LOR and photoresist.

120

HF or hydrofluoric acid is again utilized where

121

that can go into the photoresist and LOR openings in order to remove any glass on the silicon surface,

122

thereby forming a nice pathway for electrical connection.

123

For the final level in our device, we need to deposit metal to form the gate of our transistor electrical contacts,

124

as well as the capacitor itself.

125

To do this, LOR and photoresist are coated and baked, and then we can align and expose the final mass level.

126

Though this level is a bit different than our previous levels, where our previous levels were all focused on removing material.

127

With this, what we're doing now is that we're using the photoresist openings that we have

128

in order to treat them as a stencil combined with a metal deposition process.

129

A good analogy for this is that if we wanted to paint something, such as a handicap sign over here, what we might do is that we might use a stencil,

130

in this case a metal stencil, where we could deposit material by spray painting,

131

for instance, and then when we remove our stencil, we're just left with the design where we want.

132

Well, that's effectively what we're doing here at the nanoscale with the pattern that we've created.

133

But instead of spray painting, what we're actually doing is that we're effectively spraying the surface with metal atoms, in this case, aluminum here,

134

where the sample is loaded up into my sputter system, where we have argon that hits the metal target,

135

and then the metal atoms fall off and are effectively sprayed, so to speak, onto our sample.

136

So as you can see, the metal has been uniformly coated over the sample, except where there was some capped on tape at the edges there.

137

So how do we effectively remove our stencil?

138

How do we remove the photoresist layers here?

139

Well we can stick that in once again DMSO and heat that up.

140

It's always cool to see where we can start to see the metal buckle

141

and then eventually start to peel off of the surface.

142

If I apply a little bit of agitation there we can aid in its removal just leaving the pattern

143

that we want looking at it under the microscope post liftoff process what we can see is

144

that we can see our complete structure now we have the transistors the capacitors all the connections

145

that we need in order to have our DRAM array

146

if we were to look at a cross section this is the structure

147

that we have

148

and then this is how it matches up to our earlier little cartoon where we can have current flow

149

and be controlled by the transistor by our switch where it

150

can charge up our charge storage capacitor in order to hold a bit of data now as

151

if the shed wasn't enough inside in my living room i held a whole suite of test equipment

152

so i got my little lab assistant here

153

and i'm going to fire up one of these semiconductor parameter analyzes in order to look at the results.

154

Because these devices are of course at the nano scale, you can't just attach regular wires easily to them.

155

So for testing purposes, what I have set up here is

156

that I have a number of these micro manipulators with some

157

incredibly fine probe tips in order to feed electrical current

158

and voltage into the device and then be able to read that out.

159

When testing the transistor, our switch, I get the following results.

160

Each line represents a different gate voltage, where I can have different levels of current, or nearly no current depending on the gate voltage I apply.

161

This acts like our switch, or more specifically, it can act like one of those dimmer switches, where as I turn and adjust,

162

I can tune the level of output power.

163

But for RAM, we can just settle for basic on-off operation.

164

Normally, though, in a transistor, current saturates.

165

These lines stay flat.

166

It doesn't shoot up at higher voltages.

167

What we're seeing is a short channel effect known as punch-through.

168

So because the source and drain are less than one micron away from each other,

169

as we increase the voltage that we apply, they can effectively merge.

170

and this leads to an increase in current and a loss of gate control.

171

Now this is fine as long as we operate our devices at lower voltages, but it certainly shows the challenges of scaling.

172

So let's look at the other half of the equation, the charge storage capacitor that we have.

173

So here I have a CV plotter, which is a very sensitive instrument for reading up the capacitance as I

174

scan through and then vary the voltage across the capacitor

175

because the capacitor will have a minimum and a maximum capacitance of course in

176

which it can store and that maximum capacitance I recorded as 12.3 picofarads

177

which is pretty close to the perfect ideal theoretical of a little bit less than 15 picofarads

178

which I had designed for looking at them together now as one individual DRAM cell,

179

the transistor can very rapidly and quickly charge up our charge storage capacitor to 3 volts within a couple hundred nanoseconds,

180

which is great, and then it'll hold that voltage on there

181

but it'll slightly bleed off over time where we can only hold

182

that charge on there for a little bit over two milliseconds before it's completely done for.

183

We need to charge it back up if not sooner.

184

Commercial DRAM can hold its charge for greater than 64 milliseconds, so in this design it needs to be refreshed at a higher frequency.

185

Okay, this is awesome.

186

First time ever RAM has been made at home, but while you can store data on it, you can't run DOOM on it quite yet.

187

This is just a few cells to prove it can work.

188

The next step is to take these cells, to stitch them together in order to make a much larger array.

189

Then we can hook it up to a PC.

190

Stay tuned.

191

Massive thanks to everyone subscribed on Patreon who helped support this work.

192

Link below.

下載應用

流利口語所需的一切

AI 發音評分逐句打分

音標練習掌握每個音

詞彙學習建立你的詞庫

詞彙遊戲邊玩邊學

掃碼

Download on theApp Store Get it onGoogle Play

FOR YOU

背景與背景

在這個影片中，講者探討了如何在家自制RAM，面對如今因人工智慧迅速發展而引起的RAM價格飆升。他強調了半導體制造業的複雜性以及市場上幾家公司對整個行業的控制。通過將後院的一個小棚改造成潔淨室，講者展示了一種新穎且富有創造性的方式來嘗試自己製造半導體。這一過程不僅需要太多的時間和金錢，還涉及大量技術知識。因此，瞭解這一主題能幫助英語學習者在科技領域中更有效地進行交流。

日常溝通的五個關鍵短語

半導體制造 - 瞭解這一過程可以幫助你在科技相關的談話中游刃有餘。
潔淨室 - 這是專業術語，適用於談論高科技環境和裝置。
矽片清理 - 涉及一個關鍵的工藝流程，能夠展示你對技術細節的掌握。
光刻膠 - 這一技術術語會在科技術語交流中頻繁出現。
溫度控制 - 在討論製造過程中常常提到的重要引數。

逐步影子跟讀指南

在觀看此影片時，你可以通過英語影子跟讀方法來提高你的語言能力。首先，注意講者的發音和語調。可以按照以下步驟進行練習：

選擇一段你感興趣的內容，最好是影片開頭，以便於快速抓住主題。
首先聽一遍，理解大意。然後暫停，重複每一句話，嘗試模仿講者的發音。特別注意技術性詞彙的正確發音。
利用影片中的術語，進行英語口語練習。嘗試用這些詞彙進行造句，例如：“我在家裡嘗試製作半導體。”
用shadow speak的方法，逐句跟隨講者的節奏，練習到能夠流利為止。在這個過程中，努力提高發音和語調的準確性。
最後，可以與學習夥伴交流你所學到的知識，並採取雅思口語練習中所使用的技術進行互動。

通過這些方法，你不僅能提升提高英語發音的能力，還能在高科技和工程領域內提升自己的專業英語水平，助力未來的職業發展。

影片中的語法

說話人最常用的結構，並附上影片中的原話：

結構	影片中的用法
被動語態 be + 過去分詞 — 強調發生了什麼，而不是誰做的	can be detected · are made · is meant
現在完成時 have/has + 過去分詞 — 過去發生但與現在仍有關聯的事	have been · it's been · we've created
定語從句 who / which + 從句 — 補充說明人或事物	chips, which is · solution which is · salt which is

什麼是跟讀法？

跟讀法 (Shadowing) 是一種有科學依據的語言學習技巧，最初開發用於專業口譯員的培訓，並由多語言者Alexander Arguelles博士普及。這個方法簡單而強大：您在聽英語母語原聲的同時立即大聲重複——就像是一個延遲1-2秒緊跟說話者的影子。與被動聽力或語法練習不同，跟讀法強迫您的大腦和口腔肌肉同時處理並模模擬實的講話模式。研究表明它能顯著提高發音準確性，語調，節奏，連讀，聽力理解和口語流利度——使其成為雅思口語備考和真實英語交流最有效的方法之一。

影子跟讀法: 閱讀完整分步指南 →

跟讀練習: Making RAM at Home - 通過影片學習英語口語

選擇練習模式

下載應用

推薦影片

How are Microchips Made? 🖥️🛠️ CPU Manufacturing Process Steps

Wrote My Own Memory Allocator (and ran DOOM with It)

How to Make Anything - Learn to Think Like an Engineer

Understanding BGA Pads: Solder Mask Defined vs Non-Defined

Expensive RTX 5090 for LLMs? NO. Use This Instead. (Tesla V100 SXM2 + Z8 G4, #RACERRRZ)

How to do ACTIVE RECALL Effectively? (4 Techniques worked for me)

Deep Dive: Investigating Thermal Cycling Failures Cracked MSOP Solder Joints

What happens to old electronic devices when you upgrade?

Exposing The Flaw In Our Phone System

How do microSD Cards Store 2 TB in such a TINY space?

What is SMT (Surface Mount Technology)? PCB Assembly (Part 1)

Intel chips can’t possibly be this bad… 100% crash rate?

背景與背景

日常溝通的五個關鍵短語

逐步影子跟讀指南

影片中的語法

什麼是跟讀法？