शैडोइंग अभ्यास: Physical design tutorial with Cadence Innovus [basic] - वीडियो के साथ अंग्रेजी बोलना सीखें

अभ्यास मोड चुनें

हर मोड पूरी स्क्रीन का अभ्यास कक्ष खोलता है।

407 वाक्य

यदि वाक्य बहुत छोटे या लंबे हों, तो समायोजित करने के लिए Edit पर क्लिक करें।

Welcome to this physical design tutorial with Cadence Novos.

This is intended for people that are just getting started with physical design, so it's a very basic tutorial, okay?

In terms of contents, this is what we're going to be talking about.

We're going to start with setup, how do we load the design and how do we use the GUI effectively.

Then we're going to talk about floor planning and power planning.

Then we switch to the implementation steps that is placement clock tree synthesis

and routing okay to set the stage right a couple things

i gotta mention the version of innovas we're going to be using is version 21 it works fine

if you have a slightly older

or slightly newer version of innovas the commands remain mostly the same uh we'll also assume

you know a little bit about tickle

because we're going to be using a script a tickle script the design

we're going to be using is sha256 same design

that we use in the logic synthesis tutorial

you don't have to understand the design to follow this tutorial

it's just a design for us the library

we're going to be using is a seven nanometer library

it's called asap7 it is included in the repo

there's no nda concerns whatsoever you you can get access to the library right away.

Okay.

In terms of setup, how do we load the design?

How do we get started?

We got to tell the tool how to find several files, including the design itself, meaning a netlist,

the standard cell library, meaning

Liberty and left files that contain timing, power, and some notion of a abstract layout for the cells.

We have a technology left file that tells the tool what the metal stack looks like, what are the sizes of the metals,

what are the valid spacing, and all sorts of other rules for how to draw metals.

We also have timing conditions that are provided to the tool using two files, MMMC and SDC.

User constraints, like the clock period, we typically put them in the SDC file, okay?

Let's look at the script and how we handle this initialization part using a script.

So I have my script here on the top right.

Basically what we're looking for are variables that have this prefix in it.

These are special variables where the information that you put there, Inovus will treat it in a certain special way.

For instance, this one, initVariLog.

This is where you pass the netlist file to Inovus, okay?

there's a couple other ones that are interesting top cell

if you have a hierarchical design

you gotta tell the tool who is the top level of your hierarchy where does it start right

so in our case it's sha256

we also gotta tell the location of several files all the left files for instance are declared here

and all of this gets read in by the tool when we issue this command here init design.

What do you get after you initialize the design?

You get this empty canvas here on the left.

This is the GUI.

We're going to be doing a lot of work here on the GUI.

Inovus is a very graphical tool, which is very different from what we did in Genus that we were mostly using the terminal.

Now let's have a look at the shortcuts that we have.

These are important so we can use the GUI effectively.

We do a lot with the mouse wheel and then we use the keys F, K, Shift -K, A.

We also use the numbers and there's only one thing

that we don't use that is undo and redo

so let me go back to the graphical interface

so I can show you these okay so the undo

and redo are here we do not use them

because they're not consistent

if you do for instance a placement solution

you cannot undo a placement solution small changes on the floor plan you can undo

but in any case we're not going to use that okay

so let's start with the mouse wheel this is what mouse wheel does zoom in

and zoom out if i press f i have zoom to fit

if i press k i get a ruler and i click

and i click and i can measure things i can also get rid of all the rulers

and i can go back to selection mode this is the default mode right

if yeah if i had any cells

or wires here i would be selecting them right now

and that's pretty much what we need to understand the gui at this point Very well.

What do we have at this point?

We have this initial empty canvas, okay?

There's a couple strange things about this canvas.

First thing is it has a lot of horizontal gray lines.

What are those lines?

How was the size of this canvas decided?

What does it mean, right?

How did the tool draw something for me

if I didn't tell the dimensions of this canvas where I'm gonna place my design?

but also you know how is power going to be distributed

this looks like a uniform canvas that's not how power distribution works

and what happened to my pins these are all the questions

that we got to ask for getting an initial floor plan done

so let's switch to the gui view

so first thing I want to mention is the horizontal lines why do we have all those lines

that appear to run everywhere these are the rows for the

standard cells the cells are going to be placed here in this region in the rows

you can see these little triangles here these are markers for the orientation of the cells so

if i place a cell in this row

it's going to have vss at the bottom vdd at the top on the next row we flip

so we're going to have vdd vss

and we keep alternating like this this is how standard cell based design typically is done okay

now why why was this size picked why is the floor plan more

or less 180 by 180 the reason for this is

that the tool has a default of 70 percent density

and i'm gonna go to the terminal and use the command check place and we can see right here placement density 70%.

We haven't placed anything yet.

This is just an estimate.

This is the default behavior.

It doesn't mean 70 % is good or bad.

For some designs, it might be incredibly challenging to do 70%.

For some designs, it might be incredibly easy to do 70%.

But the point is that we decide the number, right?

100

We have a certain goal for our design.

101

So we have to decide how do we do that, okay?

102

we do that by uh doing our own floor plan

103

if you follow the script there's uh several uh constants here

104

and some formulas for how we're gonna decide the size for the floor plan

105

now none of this is rocket science so you can go through the script

106

and figure out what's uh what's happening there

107

but our initial floor plan now looks like this we have decided

108

that our floor plan should be more or less 190 by 190

109

but more importantly we left a little bit of empty space here on the periphery

110

that's where our power rings are going to be placed okay one other thing I wanted to mention,

111

let me get rid of all this, is the pins.

112

So we also have to decide where the pins are going to be placed.

113

That's our job as a designer.

114

The default behavior is to put all pins here on this corner, on the left, bottom left.

115

We can see there's a lot of text, overlapping text.

116

These are all the pins that are placed there, overlapping each other.

117

So next we're going to have to solve that and decide where to put those pins.

118

All right, let's fix those pins.

119

First thing I'm going to do, I'm going to hit resume on the terminal.

120

So the way this tutorial is organized, this script that was provided to you, it will suspend execution at several points during the flow.

121

This is on purpose.

122

So what you can do is just hit resume, resume, resume, and we'll keep going

123

so i'm gonna hit resume twice i'm gonna skip this step

124

it's about some physical cells that's a bit more advanced don't worry about

125

that let's just go to the pins

126

and place the pins on the edges of the design there we go

127

so now we have our pins there's a convention

128

that has been used here that our inputs are on the left

129

and our outputs are on the right this is just convention

130

Now you have to think about this in terms of a block design versus a chip design.

131

This is just a block in isolation.

132

We do not have any constraints from the top level limiting which edges we can use and which edges we cannot use.

133

But it's very easy to imagine

134

that in a large design maybe we cannot use the left

135

because there's something else there and we've got to put out the input pins on the top right.

136

This type of decision is very very common.

137

But But for us here in this tutorial, we're going to follow convention inputs on the left, outputs on the right.

138

Cool.

139

So now things are getting interesting because we're starting to actually draw things on this layout.

140

We're gonna do our power plan.

141

Okay.

142

What's the idea of the power plan?

143

We want to achieve more or less uniform distribution of power across the entire design.

144

How do we do that?

145

We form a mesh for vdd

146

and vss it's kind of a uniform grid a mesh for distributing vdd

147

and vss why do we do that

148

or standard cells assume they're gonna have stable levels of vdd

149

and vss when they are computing something so we got to make sure

150

that is true so all the timing characterization and all the power characterization that was done for those cells is actually valid.

151

What are the components of the mesh that we're going to build?

152

We're going to be using four different components.

153

We're going to put rings around the design on the periphery.

154

We're going to have vertical stripes and horizontal stripes on the upper metal layers.

155

And we're going to have power rails on the lower metal layers let's visualize what

156

that looks like this is what my power mesh looks like

157

so i start with the rings for vdd

158

and vss what are the tuning knobs

159

that i have for those rings

160

i can decide the width of the metal for those i can decide the spacing between the rings

161

and i can also decide the offset with respect to the core boundary for those rings

162

it can be zero zero is a valid number

163

but sometimes there are problems overlapping pins on top of the power rings

164

and it is also typical to leave a little bit of an offset

165

there okay then we have the vertical stripes and horizontal stripes

166

on the upper metal layers what are the tuning knobs what do we have to decide

167

we have to decide the width of the stripes the spacing between the pair right

168

they come in pairs with the dvss you you gotta decide the space in between the pair

169

and you gotta decide the pitch between pairs.

170

Okay, so three knobs that you have for the stripes.

171

Finally, using typically M1, we do the power rails.

172

They are the fin lines here on these diagram, okay?

173

They actually deliver power to the standard cells.

174

That's why they are on M1 because the cells expect power to be delivered on M1.

175

Okay, let's switch to the Inova's view, and this is our current floor plan.

176

We're going to hit resume a couple of times.

177

We have our rings now, and the rings are using metal 6.

178

I'm turning off and on metal 6, and also metal 7, okay?

179

It's common to use these alternating metals for horizontal direction and vertical direction.

180

Let's resume again now we have vertical stripes in metal 3

181

we can see here the width of the stripe the spacing between the sets

182

and the set to set distance okay the set to set

183

distance tends to be much larger than the spacing let's hit resume again

184

then we get our horizontal stripes pretty much the same idea

185

but horizontally and then we hit resume again

186

and we run a command called special route when we do

187

that what we get are all these blue lines in meta 1 delivering VDD

188

and VSS to the standard cells what else is interesting to note here every time one of these stripes

189

or rails cross each other

190

we're going to have vias being dropped to make the connection for instance

191

this right here we have the power rail in m1 crossing a vss vertical stripe

192

so this is a vss power rail this is a vss power stripe

193

when they cross a via gets dropped to make a connection okay we have vias here too between horizontal stripes

194

and vertical stripes but basically what we achieve at this point is a homogeneous balance power distribution

195

right

196

so we have the floor plan we have the power plan

197

we're ready to start actual implementation the first thing

198

we've got to do is placement the goal of placement is to find

199

valid coordinates for all the cells in our design

200

so there cannot be any overlaps okay cells cannot be on top of other cells

201

but we do that while minimizing wire length so we're gonna arrange the cells in a way that we need them

202

least amount of connections, wires running between cells.

203

And we also have to pay attention to timing the critical paths.

204

We want to make sure that cells that are on a critical path are close to each other.

205

So there's very little wiring needed.

206

That means less capacitance, better timing.

207

Now, while we're minimizing wire length, we gotta actually be a little bit smart about it

208

because just minimizing wire length is not enough

209

we gotta be aware of congestion there can be hot spots where wires are very short

210

but we can't just route them okay

211

so placement is inherently congestion aware

212

it has to be from a designer point of view what are the tuning knobs

213

that we have the biggest one is the floor plan dimensions depending on how you size the floor plan

214

you're gonna get a different placement utilization right and

215

that in turn becomes your congestion metric pretty much there's another important knob

216

that you can control which metal layers are available for signal routing you can limit

217

which ones are available in this tutorial work allowing signal routing

218

from metal 2 out the way to metal 7 okay in

219

our script what does it mean placement is one uh

220

so -called super command it's called place of pt design it's gonna do concurrent placement optimization in many rounds

221

and it keeps improving improving improving okay let's try to visualize what placement is actually doing.

222

So placement will first take the net list and consider it as a graph.

223

You know there are these connections between these nodes of the graph

224

but you know these connections don't have a notion of distance

225

so it's some notion of an abstract cost of having those logical connections

226

but when you turn them into electrical connections they actually have a physical cost

227

so first thing the placement will do is find locations for the cells put them on a grid right

228

this is a regular grid here

229

and then it will make some notion of an estimate of how to connect all these cells

230

that have to be connected to each other okay that estimate at some point has to turn into actual routing.

231

So first thing here to notice, we have some green lines, the estimates, that are basically running on the diagonals.

232

There's no diagonal routing in modern technologies, so we gotta do only horizontal and vertical routing.

233

So we can take a look at this connection here between D and H and became this 90 degree turn,

234

okay? what else is interesting to notice here look at this connection between a and d

235

because we cannot have 45 degree wire running there we are pretty much obliged to switch to a higher metal

236

so we cannot use this blue lines

237

because they're all taken all the resources available are taken

238

or I can do something a little bit different

239

I could move C to the left to create some space for A to connect to D

240

and C still remain connected to A but that means my floor plan now

241

sorry my placement position now has a gap here

242

this is typical these are the decisions

243

that the placement engine is trying to do for you

244

and it's able to do this very effectively for designs with millions of gates and will give you a solution that

245

is good for timing it's good for wire length

246

it's good for powers it's good for everything

247

it's optimized across the board right here is what we get in the gui after we run the place opt command

248

first thing we notice right away is

249

that there is a lot of wires here right i can and I can't even see the cells underneath all the wires.

250

How is this possible?

251

I'm running a placement step, but it seems that routing was done.

252

Well, routing was not done.

253

This is just an estimated routing that is needed because placement is congestion aware, okay?

254

So none of this is committed route.

255

These are just estimates, but I can go ahead

256

and hide all of these metals

257

so we can take a look at the actual placement solution

258

this is what it looks like we can see some areas

259

here in this region appear to be really dense maybe some

260

areas here on the top are not as dense right

261

i can zoom in here we can see a lot of empty spaces

262

if i zoom in here it seems like i have very small empty spaces but there's still some

263

what else can i do at this point i can check my density

264

so it is about 52 .5 that's fine it should be very likely a routable design at this density

265

but i can also do other checks before i move

266

forward i can for instance do report timing to see

267

if i'm meeting timing and i i am i have a slack of

268

20 picoseconds so this is fine i could also check power

269

if i have a strict power budget i could check it now to see

270

if i'm still under my budget and if i'm not or

271

if i'm not meeting timing i could make changes to my placement changes to my floor plan before moving forward

272

after placement the next step is the clock tree synthesis

273

and this step the goal is to deliver the clock signal to every flip -flop more or less at the same time.

274

It doesn't have to be precisely at the same time, but more or less at the same time.

275

And we do that while minimizing cost.

276

Primarily we worry about power with the clock tree.

277

The reason why we worry about power is because the implementation of the clock tree is a tree of buffers.

278

Every time the clock signal toggles these buffers are toggling as well

279

if we build a clock tree that is over provided

280

that has too many buffers

281

we're burning power for no good reason okay in terms of tuning knobs there are two big ones

282

that is the depth and the skew the depth is also called the insertion delay

283

and the skew is the difference between arrival time of the clock in two different flip -flops

284

or the largest difference between any two flip -flops on the clock tree.

285

For the sake of implementation, this is all done with single command.

286

In OVOS, CC OPT design, we'll do concurrent synthesis of the clock tree and timing optimization of the regular paths.

287

Let's visualize the clock tree and its properties.

288

This is basically what we have.

289

we have the clock source here in green

290

and then we have all the sinks

291

which are the clock pins of the flip -flops okay

292

this clock tree here in this illustration

293

it is balanced the branches have the same depth

294

they didn't have to have the same depth the tree can

295

be unbalanced insertion delay is measured from the green pin all

296

the way to the clock pin of a flip -flop

297

and we look for basically the longest delay from the source to all the flip -flops

298

and that's our insertion delay and we try to minimize

299

that in terms of skew we look at a pair of flip -flops

300

and we measure the difference between the arrival time of the clock on those two

301

and we try to minimize that skew or sometimes we try to borrow skew

302

so we try to maximize on purpose to kind of it's a form of retiming almost

303

we try to cheat a little bit by doing that okay

304

but let's look at these two flip flops here

305

and the skew arrow how is it possible

306

that the clock is going to arrive at the different times well this buffer is different than this buffer

307

so they can have different sizes even

308

if have the same size they're susceptible to process variation

309

so the actual arrival time is different or can be different right so clock tree synthesis takes that into account

310

let's go back to the gui

311

and see what our clock tree looks like at first our design looks about the same

312

we can't really see any immediate differences

313

so what i'm going to do is i'm going to hide every signal routing

314

and every power and ground routes okay so now what is left is

315

the clock tree basically you can see these branches that fan out and kind of age shapes

316

this is very normal for a clock tree

317

we can see where the clock tree starts right here

318

this is our clock pin there you go that's our clock and it gets distributed all over the place

319

we can also see where the buffers are we have these two cells here marked in blue

320

these are buffers we can see there the prefix buff that's definitely a buffer

321

we can look at the other one here again that's a buffer there's a an even better way to visualize

322

what the clock tree looks like under the clock menu here on the top

323

there's an option called clock tree debugger once you open

324

that you get a window that looks like this okay this is the clock tree debugger

325

so it shows you very clearly the tree shape of the clock tree uh all these triangles here they're buffers

326

and the red squares at the bottom they are the flip -flops

327

so you can see how more

328

or less everything is balanced some branches have you know not the same fan out as other branches

329

but in terms of depth we do have a very balanced clock tree there's a lot of reporting commands

330

that you can do to get finer properties of the clock tree including the two properties

331

that i mentioned insertion delay

332

and the skew we're very close to done the final step

333

for us is routing okay the goal here is to connect every signal wire

334

we already connected power we already connected clock we give those priority naturally

335

now what's left to connect are the signals when do

336

that we gotta make sure

337

we respect all the routing rules for this technology all the spacings all the valid widths

338

and all that we also do routing while trying to minimize delay minimize power

339

and we also gotta observe pay attention to signal integrity issues like crosstalk between wires are also very important

340

this type of the flow is time consuming okay more time consuming in what came before

341

but also convergence problems they tend to happen at this stage

342

you reach a routing solution it has a couple DRC violations you do a couple changes then those violations disappear

343

and a few new ones appear and you can spend considerable time chasing these violations

344

and not really converging to a final solution in terms of tuning knobs

345

that the designer has available to him you obviously have to decide the metal layers that are allowed for routing

346

but the routing engine also has a notion of effort

347

it iterates it has a notion of steps you can increase the ceiling for the max number of steps

348

so we'll keep trying longer

349

if it fails to find a valid uh drc free solution

350

for routing all of this is done in an office with

351

a single super command called route design in terms of violations

352

and what you should be watching out for you know every technology is a little bit different

353

but most of the time when you have drc violations

354

these are the common cases so you have spacing issues

355

when two nets on the same metal layer different nets

356

but same metal layer they violate the minimum spacing between them right

357

this spacing is not a constant it's context aware

358

it depends on how thick those metals are for how long they run in parallel

359

and a bunch of other more advanced things like color

360

if the technology has coloring the rules for spacing can be very complicated

361

sometimes you cannot look at a single pair of nets you got to look at a triplet

362

and the rules become quite complicated

363

but what you see as a violation in the end is a spacing violation

364

if your design has congestion problems what you will eventually see are shorts the router will give you a solution

365

but two wires of different nets cross each other creating a short right this shouldn't happen

366

Here's what we get after we are done running the routing command.

367

We get a total of five violations for this design.

368

We can see them on the terminal.

369

They're listed here in this table format.

370

We can see this is an acronym for metal spacing.

371

We have one metal spacing issue in metal 3.

372

We have a couple of shorts in metal 2

373

and we have an end of line problem also in metal 3 for a total of five violations.

374

We can inspect them using the graphical interface and decide what to do, how to fix them.

375

Let's zoom in on this little white X here that's a violation.

376

We can't really see much, we can't really understand what's going on.

377

So I know this violation is either metal 2 or metal 3, so i'm gonna start hiding metals

378

that are not involved in this violation let's get rid of this let's get rid of this

379

and this okay uh

380

so what's happening here this is a short how do i know this is a short

381

because i see a net here it's called n2603

382

and it is connected to a net called core n48 something they're different nets they shouldn't be connected

383

so this is obviously a short okay this is one of the problems we have now

384

the next step for a designer would be to fix those violations

385

there can be advanced ways of fixing these violations including ECO

386

and other things but the most interesting thing is the fixing sometimes can be easy

387

but what a good designer actually has to do is identify

388

the patterns why these violations are happening why they're there in the first place

389

so let me first enable all the metals again

390

and we're going to zoom in on these violations one by one

391

and see what's happening

392

so we already did this one we saw it was a short there let's have a look at this one

393

let's get rid of metal one and rid of four

394

and five okay here's our violation it's not

395

that far from the other one okay interesting let's look at this one here on the top

396

here it is there's a pattern here and i'm not sure

397

if you were able to see this right away but these violations

398

that we have they're always next to a stripe

399

this is a vdd stripe let's go back to the other ones

400

you see here right next to a vdd stripe right next to a vss stripe

401

this is somewhat natural

402

because these stripes are really big pieces of metal they take a lot of routing resources

403

so that zone becomes depleted of routing resources and violations can appear there

404

but that's the pattern i was talking about once you identify the pattern fixing the drc is this relatively easy

405

that being said we're going to stop this video here

406

this is the end of the tutorial i'm planning on doing more advanced videos

407

but for this tutorial this is it thank you

ऐप डाउनलोड करें

धाराप्रवाह बोलने के लिए ज़रूरी सब कुछ

AI उच्चारण स्कोरहर वाक्य का स्कोर

IPA अभ्यासहर ध्वनि में महारत

शब्दावलीअपना शब्द भंडार बनाएँ

शब्द गेमखेलते हुए सीखें

QR स्कैन करें

Download on theApp Store Get it onGoogle Play

FOR YOU

अनुशंसित वीडियो

96 वाक्य

🔥Launching Analog VLSI Mastery : Cohort (0-100) || A Complete Placement Guide || Himanshu Agarwal

Daily ConversationUniversity Students

107 वाक्य

Engineer's tool list

Daily ConversationUniversity StudentsWorking Adults

76 वाक्य

GC FID Operational Tutorial

Daily ConversationUniversity Students

37 वाक्य

How to Make a Mind Map - The Basics

Daily ConversationUniversity StudentsWorking Adults

400 वाक्य

Physics Informed Neural Networks (PINNs) [Physics Informed Machine Learning]

Daily ConversationUniversity Students

331 वाक्य

Dear Higgsfield, I reverse engineered you in 12 hours

Daily ConversationUniversity StudentsWorking Adults

113 वाक्य

Architectural Design Process Explained

Daily ConversationUniversity StudentsWorking Adults

7 वाक्य

Diodes Explained - The basics how diodes work working principle pn junction

Daily ConversationUniversity StudentsWorking Adults

111 वाक्य

[Lecture Ready3] Ch10 Lecture2

Daily ConversationUniversity Students

इस पाठ की शब्दावली और बोलने के सुझाव

यह स्पीकिंग पाठ वीडियो “Physical design tutorial with Cadence Innovus” पर आधारित है। सबसे ज़्यादा दोहराए गए शब्द ये हैं: clock, metal, design, cell, tree। इस वीडियो में शैडोइंग के लिए 407 वाक्य और 4911 शब्द हैं। बोला गया हिस्सा 32:29 लंबा है। वक्ता लगभग 151 शब्द प्रति मिनट की स्वाभाविक गति से बोलता है, जो रोज़मर्रा की बातचीत के करीब है। केवल 81% शब्द अंग्रेज़ी के 3,000 सबसे आम शब्दों में से हैं, इसलिए शब्दावली कठिन है।

इस वीडियो की मुख्य शब्दावली

वीडियो के 15 सीखने लायक शब्द, उच्चारण और अर्थ के साथ:

शब्द	उच्चारण	अर्थ
wire संज्ञा	/ˈwaɪɚ/	तार
pin संज्ञा	/pɪn/	पिन
script संज्ञा	/skɹɪpt/	लिपि, लेखन
horizontal विशेषण	/ˌhoɹəˈzɑn.təl/	क्षैतिज
layer संज्ञा	/ˈleɪ̯ɚ/	परत, तह
vertical विशेषण	/ˈvɝ.tɪ.kəl/	लंबवत्, ऊर्ध्वाधर
delay संज्ञा	/dɪˈleɪ̯/	देर, विलंब
notion संज्ञा	/ˈnoʊʃən/	संकल्पना
designer संज्ञा	/dɪˈzaɪnɚ/	डिज़ाइनर
estimate संज्ञा	/ˈɛs.tɪ.mət/	आकलन, अनुमान
tune संज्ञा	/tjuːn/	धुन
density संज्ञा	/ˈdɛn.sə.ti/	घनत्व
implementation संज्ञा	/ˌɪmplɪmənˈteɪʃən/	कार्यान्वयन
default संज्ञा	/dɪˈfɔlt/	व्यतिक्रम
undo क्रिया	/ʌnˈduː/	उधेड़ना

वीडियो में आने वाली फ़्रेज़ल वर्ब

शब्द	उच्चारण	अर्थ
go ahead क्रिया	/ˌɡoʊ əˈhɛd/	आगे बढ़ना
turn off क्रिया		बंद करना

दोहराने लायक वाक्य

वीडियो के छोटे, पूरे वाक्य जिन्हें आप रोज़ की बातचीत में इस्तेमाल कर सकते हैं:

How do we get started?
What do you get after you initialize the design?
What do we have at this point?
How do we do that?
What are the components of the mesh that we're going to build?

इस वीडियो का व्याकरण

वक्ता जिन संरचनाओं का सबसे अधिक प्रयोग करता है, वीडियो के असली शब्दों के साथ:

संरचना	वीडियो में
Passive voice be + past participle — ज़ोर इस पर कि क्या होता है, न कि कौन करता है	is intended · is included · are provided
Present perfect have/has + past participle — बीता हुआ काम जिसका असर अभी भी है	haven't placed · have decided · has been

ध्यान देने योग्य उच्चारण

वक्ता 100 बार संक्षिप्त रूपों का प्रयोग करता है, जैसे we're, I'm, gonna। इन्हें वैसे ही छोटा बोलें जैसा आप सुनते हैं।

“th” की ध्वनियाँ: synthesis /ˈsɪnθəsɪs/, width /ˈwɪtθ/, thick /θɪk/, underneath /ˌʌndɚˈniθ/
“sh” और “zh” की ध्वनियाँ: violation /ˌvaɪ.əˈleɪ.ʃən/, notion /ˈnoʊʃən/, implementation /ˌɪmplɪmənˈteɪʃən/, mesh /mɛʃ/, dimension /daɪˈmɛn.ʃən/
लंबे शब्द — बलाघात सही रखें: violation /ˌvaɪ.əˈleɪ.ʃən/, horizontal /ˌhoɹəˈzɑn.təl/, implementation /ˌɪmplɪmənˈteɪʃən/, complicated /ˈkɑm.plɪˌkeɪ.tɪd/, incredibly /ɪŋˈkɹɛdɪbli/

हिंदी भाषियों के लिए मुश्किल ध्वनियाँ:

/v/ और /w/ का फ़र्क़ — /v/ में ऊपर के दाँत निचले होंठ को छूते हैं, /w/ में होंठ गोल होते हैं: violation /ˌvaɪ.əˈleɪ.ʃən/, wire /ˈwaɪɚ/, vertical /ˈvɝ.tɪ.kəl/, valid /ˈvælɪd/, canvas /ˈkæn.vəs/
/z/ — इसे “ज” (/dʒ/) न बनाएँ: resume /ˈɹɛz.ə.meɪ/, horizontal /ˌhoɹəˈzɑn.təl/, minimize /ˈmɪn.ɪˌmaɪz/, zoom /zuːm/, designer /dɪˈzaɪnɚ/
शब्द की शुरुआत में s + व्यंजन — पहले “इ” न जोड़ें: stripe /stɹaɪp/, script /skɹɪpt/, stable /ˈsteɪ.bəl/, strict /stɹɪkt/, skip /skɪp/

इस वीडियो से अभ्यास कैसे करें

पहले बिना बोले पूरा वीडियो एक बार सुनें और जो शब्द नहीं आते उन्हें लिख लें।
0.75× गति से शुरू करें, एक-एक वाक्य की शैडोइंग करें, और सहज लगने पर सामान्य गति पर लौटें।
अपनी आवाज़ रिकॉर्ड करें और मूल से तुलना करें, ख़ासकर wire, pin, script जैसे शब्दों पर ध्यान दें।

शैडोइंग तकनीक क्या है?

शैडोइंग (Shadowing) एक विज्ञान-समर्थित भाषा सीखने की तकनीक है जो मूल रूप से पेशेवर दुभाषिया प्रशिक्षण के लिए विकसित की गई थी। विधि सरल लेकिन शक्तिशाली है: आप मूल अंग्रेज़ी ऑडियो सुनते हैं और तुरंत इसे ज़ोर से दोहराते हैं — जैसे वक्ता की छाया 1-2 सेकंड की देरी से। शोध से पता चलता है कि यह उच्चारण सटीकता, स्वर, लय, जुड़ी हुई ध्वनियाँ, सुनने की समझ और बोलने की प्रवाहशीलता में काफ़ी सुधार करता है।

शैडोइंग तकनीक: पूरी चरण-दर-चरण गाइड पढ़ें →

शैडोइंग अभ्यास: Physical design tutorial with Cadence Innovus [basic] - वीडियो के साथ अंग्रेजी बोलना सीखें

अभ्यास मोड चुनें

ऐप डाउनलोड करें

Design Patterns in Java Theory

PCB 101 Academy - Learn how printed circuit boards are assembled

Civil 3D course for beginners - Part 2 of 3

🔥Launching Analog VLSI Mastery : Cohort (0-100) || A Complete Placement Guide || Himanshu Agarwal

Engineer's tool list

GC FID Operational Tutorial

How to Make a Mind Map - The Basics

Physics Informed Neural Networks (PINNs) [Physics Informed Machine Learning]

Dear Higgsfield, I reverse engineered you in 12 hours

Architectural Design Process Explained

Diodes Explained - The basics how diodes work working principle pn junction

[Lecture Ready3] Ch10 Lecture2

इस पाठ की शब्दावली और बोलने के सुझाव

इस वीडियो की मुख्य शब्दावली

वीडियो में आने वाली फ़्रेज़ल वर्ब

दोहराने लायक वाक्य

इस वीडियो का व्याकरण

ध्यान देने योग्य उच्चारण

इस वीडियो से अभ्यास कैसे करें

शैडोइंग तकनीक क्या है?