Shadowing Practice: Physical design tutorial with Cadence Innovus [basic] - Learn English Speaking with Video

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Welcome to this physical design tutorial with Cadence Novos.

This is intended for people that are just getting started with physical design, so it's a very basic tutorial, okay?

In terms of contents, this is what we're going to be talking about.

We're going to start with setup, how do we load the design and how do we use the GUI effectively.

Then we're going to talk about floor planning and power planning.

Then we switch to the implementation steps that is placement clock tree synthesis

and routing okay to set the stage right a couple things

i gotta mention the version of innovas we're going to be using is version 21 it works fine

if you have a slightly older

or slightly newer version of innovas the commands remain mostly the same uh we'll also assume

you know a little bit about tickle

because we're going to be using a script a tickle script the design

we're going to be using is sha256 same design

that we use in the logic synthesis tutorial

you don't have to understand the design to follow this tutorial

it's just a design for us the library

we're going to be using is a seven nanometer library

it's called asap7 it is included in the repo

there's no nda concerns whatsoever you you can get access to the library right away.

Okay.

In terms of setup, how do we load the design?

How do we get started?

We got to tell the tool how to find several files, including the design itself, meaning a netlist,

the standard cell library, meaning

Liberty and left files that contain timing, power, and some notion of a abstract layout for the cells.

We have a technology left file that tells the tool what the metal stack looks like, what are the sizes of the metals,

what are the valid spacing, and all sorts of other rules for how to draw metals.

We also have timing conditions that are provided to the tool using two files, MMMC and SDC.

User constraints, like the clock period, we typically put them in the SDC file, okay?

Let's look at the script and how we handle this initialization part using a script.

So I have my script here on the top right.

Basically what we're looking for are variables that have this prefix in it.

These are special variables where the information that you put there, Inovus will treat it in a certain special way.

For instance, this one, initVariLog.

This is where you pass the netlist file to Inovus, okay?

there's a couple other ones that are interesting top cell

if you have a hierarchical design

you gotta tell the tool who is the top level of your hierarchy where does it start right

so in our case it's sha256

we also gotta tell the location of several files all the left files for instance are declared here

and all of this gets read in by the tool when we issue this command here init design.

What do you get after you initialize the design?

You get this empty canvas here on the left.

This is the GUI.

We're going to be doing a lot of work here on the GUI.

Inovus is a very graphical tool, which is very different from what we did in Genus that we were mostly using the terminal.

Now let's have a look at the shortcuts that we have.

These are important so we can use the GUI effectively.

We do a lot with the mouse wheel and then we use the keys F, K, Shift -K, A.

We also use the numbers and there's only one thing

that we don't use that is undo and redo

so let me go back to the graphical interface

so I can show you these okay so the undo

and redo are here we do not use them

because they're not consistent

if you do for instance a placement solution

you cannot undo a placement solution small changes on the floor plan you can undo

but in any case we're not going to use that okay

so let's start with the mouse wheel this is what mouse wheel does zoom in

and zoom out if i press f i have zoom to fit

if i press k i get a ruler and i click

and i click and i can measure things i can also get rid of all the rulers

and i can go back to selection mode this is the default mode right

if yeah if i had any cells

or wires here i would be selecting them right now

and that's pretty much what we need to understand the gui at this point Very well.

What do we have at this point?

We have this initial empty canvas, okay?

There's a couple strange things about this canvas.

First thing is it has a lot of horizontal gray lines.

What are those lines?

How was the size of this canvas decided?

What does it mean, right?

How did the tool draw something for me

if I didn't tell the dimensions of this canvas where I'm gonna place my design?

but also you know how is power going to be distributed

this looks like a uniform canvas that's not how power distribution works

and what happened to my pins these are all the questions

that we got to ask for getting an initial floor plan done

so let's switch to the gui view

so first thing I want to mention is the horizontal lines why do we have all those lines

that appear to run everywhere these are the rows for the

standard cells the cells are going to be placed here in this region in the rows

you can see these little triangles here these are markers for the orientation of the cells so

if i place a cell in this row

it's going to have vss at the bottom vdd at the top on the next row we flip

so we're going to have vdd vss

and we keep alternating like this this is how standard cell based design typically is done okay

now why why was this size picked why is the floor plan more

or less 180 by 180 the reason for this is

that the tool has a default of 70 percent density

and i'm gonna go to the terminal and use the command check place and we can see right here placement density 70%.

We haven't placed anything yet.

This is just an estimate.

This is the default behavior.

It doesn't mean 70 % is good or bad.

For some designs, it might be incredibly challenging to do 70%.

For some designs, it might be incredibly easy to do 70%.

But the point is that we decide the number, right?

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We have a certain goal for our design.

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So we have to decide how do we do that, okay?

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we do that by uh doing our own floor plan

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if you follow the script there's uh several uh constants here

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and some formulas for how we're gonna decide the size for the floor plan

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now none of this is rocket science so you can go through the script

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and figure out what's uh what's happening there

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but our initial floor plan now looks like this we have decided

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that our floor plan should be more or less 190 by 190

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but more importantly we left a little bit of empty space here on the periphery

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that's where our power rings are going to be placed okay one other thing I wanted to mention,

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let me get rid of all this, is the pins.

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So we also have to decide where the pins are going to be placed.

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That's our job as a designer.

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The default behavior is to put all pins here on this corner, on the left, bottom left.

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We can see there's a lot of text, overlapping text.

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These are all the pins that are placed there, overlapping each other.

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So next we're going to have to solve that and decide where to put those pins.

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All right, let's fix those pins.

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First thing I'm going to do, I'm going to hit resume on the terminal.

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So the way this tutorial is organized, this script that was provided to you, it will suspend execution at several points during the flow.

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This is on purpose.

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So what you can do is just hit resume, resume, resume, and we'll keep going

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so i'm gonna hit resume twice i'm gonna skip this step

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it's about some physical cells that's a bit more advanced don't worry about

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that let's just go to the pins

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and place the pins on the edges of the design there we go

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so now we have our pins there's a convention

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that has been used here that our inputs are on the left

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and our outputs are on the right this is just convention

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Now you have to think about this in terms of a block design versus a chip design.

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This is just a block in isolation.

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We do not have any constraints from the top level limiting which edges we can use and which edges we cannot use.

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But it's very easy to imagine

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that in a large design maybe we cannot use the left

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because there's something else there and we've got to put out the input pins on the top right.

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This type of decision is very very common.

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But But for us here in this tutorial, we're going to follow convention inputs on the left, outputs on the right.

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Cool.

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So now things are getting interesting because we're starting to actually draw things on this layout.

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We're gonna do our power plan.

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Okay.

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What's the idea of the power plan?

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We want to achieve more or less uniform distribution of power across the entire design.

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How do we do that?

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We form a mesh for vdd

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and vss it's kind of a uniform grid a mesh for distributing vdd

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and vss why do we do that

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or standard cells assume they're gonna have stable levels of vdd

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and vss when they are computing something so we got to make sure

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that is true so all the timing characterization and all the power characterization that was done for those cells is actually valid.

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What are the components of the mesh that we're going to build?

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We're going to be using four different components.

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We're going to put rings around the design on the periphery.

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We're going to have vertical stripes and horizontal stripes on the upper metal layers.

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And we're going to have power rails on the lower metal layers let's visualize what

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that looks like this is what my power mesh looks like

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so i start with the rings for vdd

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and vss what are the tuning knobs

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that i have for those rings

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i can decide the width of the metal for those i can decide the spacing between the rings

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and i can also decide the offset with respect to the core boundary for those rings

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it can be zero zero is a valid number

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but sometimes there are problems overlapping pins on top of the power rings

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and it is also typical to leave a little bit of an offset

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there okay then we have the vertical stripes and horizontal stripes

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on the upper metal layers what are the tuning knobs what do we have to decide

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we have to decide the width of the stripes the spacing between the pair right

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they come in pairs with the dvss you you gotta decide the space in between the pair

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and you gotta decide the pitch between pairs.

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Okay, so three knobs that you have for the stripes.

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Finally, using typically M1, we do the power rails.

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They are the fin lines here on these diagram, okay?

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They actually deliver power to the standard cells.

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That's why they are on M1 because the cells expect power to be delivered on M1.

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Okay, let's switch to the Inova's view, and this is our current floor plan.

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We're going to hit resume a couple of times.

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We have our rings now, and the rings are using metal 6.

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I'm turning off and on metal 6, and also metal 7, okay?

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It's common to use these alternating metals for horizontal direction and vertical direction.

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Let's resume again now we have vertical stripes in metal 3

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we can see here the width of the stripe the spacing between the sets

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and the set to set distance okay the set to set

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distance tends to be much larger than the spacing let's hit resume again

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then we get our horizontal stripes pretty much the same idea

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but horizontally and then we hit resume again

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and we run a command called special route when we do

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that what we get are all these blue lines in meta 1 delivering VDD

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and VSS to the standard cells what else is interesting to note here every time one of these stripes

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or rails cross each other

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we're going to have vias being dropped to make the connection for instance

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this right here we have the power rail in m1 crossing a vss vertical stripe

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so this is a vss power rail this is a vss power stripe

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when they cross a via gets dropped to make a connection okay we have vias here too between horizontal stripes

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and vertical stripes but basically what we achieve at this point is a homogeneous balance power distribution

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right

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so we have the floor plan we have the power plan

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we're ready to start actual implementation the first thing

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we've got to do is placement the goal of placement is to find

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valid coordinates for all the cells in our design

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so there cannot be any overlaps okay cells cannot be on top of other cells

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but we do that while minimizing wire length so we're gonna arrange the cells in a way that we need them

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least amount of connections, wires running between cells.

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And we also have to pay attention to timing the critical paths.

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We want to make sure that cells that are on a critical path are close to each other.

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So there's very little wiring needed.

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That means less capacitance, better timing.

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Now, while we're minimizing wire length, we gotta actually be a little bit smart about it

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because just minimizing wire length is not enough

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we gotta be aware of congestion there can be hot spots where wires are very short

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but we can't just route them okay

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so placement is inherently congestion aware

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it has to be from a designer point of view what are the tuning knobs

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that we have the biggest one is the floor plan dimensions depending on how you size the floor plan

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you're gonna get a different placement utilization right and

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that in turn becomes your congestion metric pretty much there's another important knob

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that you can control which metal layers are available for signal routing you can limit

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which ones are available in this tutorial work allowing signal routing

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from metal 2 out the way to metal 7 okay in

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our script what does it mean placement is one uh

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so -called super command it's called place of pt design it's gonna do concurrent placement optimization in many rounds

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and it keeps improving improving improving okay let's try to visualize what placement is actually doing.

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So placement will first take the net list and consider it as a graph.

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You know there are these connections between these nodes of the graph

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but you know these connections don't have a notion of distance

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so it's some notion of an abstract cost of having those logical connections

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but when you turn them into electrical connections they actually have a physical cost

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so first thing the placement will do is find locations for the cells put them on a grid right

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this is a regular grid here

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and then it will make some notion of an estimate of how to connect all these cells

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that have to be connected to each other okay that estimate at some point has to turn into actual routing.

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So first thing here to notice, we have some green lines, the estimates, that are basically running on the diagonals.

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There's no diagonal routing in modern technologies, so we gotta do only horizontal and vertical routing.

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So we can take a look at this connection here between D and H and became this 90 degree turn,

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okay? what else is interesting to notice here look at this connection between a and d

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because we cannot have 45 degree wire running there we are pretty much obliged to switch to a higher metal

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so we cannot use this blue lines

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because they're all taken all the resources available are taken

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or I can do something a little bit different

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I could move C to the left to create some space for A to connect to D

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and C still remain connected to A but that means my floor plan now

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sorry my placement position now has a gap here

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this is typical these are the decisions

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that the placement engine is trying to do for you

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and it's able to do this very effectively for designs with millions of gates and will give you a solution that

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is good for timing it's good for wire length

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it's good for powers it's good for everything

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it's optimized across the board right here is what we get in the gui after we run the place opt command

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first thing we notice right away is

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that there is a lot of wires here right i can and I can't even see the cells underneath all the wires.

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How is this possible?

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I'm running a placement step, but it seems that routing was done.

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Well, routing was not done.

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This is just an estimated routing that is needed because placement is congestion aware, okay?

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So none of this is committed route.

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These are just estimates, but I can go ahead

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and hide all of these metals

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so we can take a look at the actual placement solution

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this is what it looks like we can see some areas

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here in this region appear to be really dense maybe some

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areas here on the top are not as dense right

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i can zoom in here we can see a lot of empty spaces

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if i zoom in here it seems like i have very small empty spaces but there's still some

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what else can i do at this point i can check my density

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so it is about 52 .5 that's fine it should be very likely a routable design at this density

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but i can also do other checks before i move

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forward i can for instance do report timing to see

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if i'm meeting timing and i i am i have a slack of

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20 picoseconds so this is fine i could also check power

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if i have a strict power budget i could check it now to see

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if i'm still under my budget and if i'm not or

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if i'm not meeting timing i could make changes to my placement changes to my floor plan before moving forward

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after placement the next step is the clock tree synthesis

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and this step the goal is to deliver the clock signal to every flip -flop more or less at the same time.

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It doesn't have to be precisely at the same time, but more or less at the same time.

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And we do that while minimizing cost.

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Primarily we worry about power with the clock tree.

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The reason why we worry about power is because the implementation of the clock tree is a tree of buffers.

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Every time the clock signal toggles these buffers are toggling as well

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if we build a clock tree that is over provided

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that has too many buffers

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we're burning power for no good reason okay in terms of tuning knobs there are two big ones

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that is the depth and the skew the depth is also called the insertion delay

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and the skew is the difference between arrival time of the clock in two different flip -flops

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or the largest difference between any two flip -flops on the clock tree.

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For the sake of implementation, this is all done with single command.

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In OVOS, CC OPT design, we'll do concurrent synthesis of the clock tree and timing optimization of the regular paths.

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Let's visualize the clock tree and its properties.

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This is basically what we have.

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we have the clock source here in green

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and then we have all the sinks

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which are the clock pins of the flip -flops okay

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this clock tree here in this illustration

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it is balanced the branches have the same depth

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they didn't have to have the same depth the tree can

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be unbalanced insertion delay is measured from the green pin all

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the way to the clock pin of a flip -flop

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and we look for basically the longest delay from the source to all the flip -flops

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and that's our insertion delay and we try to minimize

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that in terms of skew we look at a pair of flip -flops

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and we measure the difference between the arrival time of the clock on those two

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and we try to minimize that skew or sometimes we try to borrow skew

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so we try to maximize on purpose to kind of it's a form of retiming almost

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we try to cheat a little bit by doing that okay

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but let's look at these two flip flops here

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and the skew arrow how is it possible

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that the clock is going to arrive at the different times well this buffer is different than this buffer

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so they can have different sizes even

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if have the same size they're susceptible to process variation

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so the actual arrival time is different or can be different right so clock tree synthesis takes that into account

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let's go back to the gui

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and see what our clock tree looks like at first our design looks about the same

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we can't really see any immediate differences

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so what i'm going to do is i'm going to hide every signal routing

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and every power and ground routes okay so now what is left is

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the clock tree basically you can see these branches that fan out and kind of age shapes

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this is very normal for a clock tree

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we can see where the clock tree starts right here

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this is our clock pin there you go that's our clock and it gets distributed all over the place

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we can also see where the buffers are we have these two cells here marked in blue

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these are buffers we can see there the prefix buff that's definitely a buffer

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we can look at the other one here again that's a buffer there's a an even better way to visualize

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what the clock tree looks like under the clock menu here on the top

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there's an option called clock tree debugger once you open

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that you get a window that looks like this okay this is the clock tree debugger

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so it shows you very clearly the tree shape of the clock tree uh all these triangles here they're buffers

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and the red squares at the bottom they are the flip -flops

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so you can see how more

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or less everything is balanced some branches have you know not the same fan out as other branches

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but in terms of depth we do have a very balanced clock tree there's a lot of reporting commands

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that you can do to get finer properties of the clock tree including the two properties

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that i mentioned insertion delay

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and the skew we're very close to done the final step

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for us is routing okay the goal here is to connect every signal wire

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we already connected power we already connected clock we give those priority naturally

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now what's left to connect are the signals when do

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that we gotta make sure

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we respect all the routing rules for this technology all the spacings all the valid widths

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and all that we also do routing while trying to minimize delay minimize power

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and we also gotta observe pay attention to signal integrity issues like crosstalk between wires are also very important

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this type of the flow is time consuming okay more time consuming in what came before

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but also convergence problems they tend to happen at this stage

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you reach a routing solution it has a couple DRC violations you do a couple changes then those violations disappear

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and a few new ones appear and you can spend considerable time chasing these violations

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and not really converging to a final solution in terms of tuning knobs

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that the designer has available to him you obviously have to decide the metal layers that are allowed for routing

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but the routing engine also has a notion of effort

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it iterates it has a notion of steps you can increase the ceiling for the max number of steps

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so we'll keep trying longer

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if it fails to find a valid uh drc free solution

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for routing all of this is done in an office with

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a single super command called route design in terms of violations

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and what you should be watching out for you know every technology is a little bit different

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but most of the time when you have drc violations

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these are the common cases so you have spacing issues

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when two nets on the same metal layer different nets

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but same metal layer they violate the minimum spacing between them right

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this spacing is not a constant it's context aware

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it depends on how thick those metals are for how long they run in parallel

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and a bunch of other more advanced things like color

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if the technology has coloring the rules for spacing can be very complicated

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sometimes you cannot look at a single pair of nets you got to look at a triplet

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and the rules become quite complicated

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but what you see as a violation in the end is a spacing violation

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if your design has congestion problems what you will eventually see are shorts the router will give you a solution

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but two wires of different nets cross each other creating a short right this shouldn't happen

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Here's what we get after we are done running the routing command.

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We get a total of five violations for this design.

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We can see them on the terminal.

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They're listed here in this table format.

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We can see this is an acronym for metal spacing.

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We have one metal spacing issue in metal 3.

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We have a couple of shorts in metal 2

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and we have an end of line problem also in metal 3 for a total of five violations.

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We can inspect them using the graphical interface and decide what to do, how to fix them.

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Let's zoom in on this little white X here that's a violation.

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We can't really see much, we can't really understand what's going on.

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So I know this violation is either metal 2 or metal 3, so i'm gonna start hiding metals

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that are not involved in this violation let's get rid of this let's get rid of this

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and this okay uh

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so what's happening here this is a short how do i know this is a short

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because i see a net here it's called n2603

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and it is connected to a net called core n48 something they're different nets they shouldn't be connected

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so this is obviously a short okay this is one of the problems we have now

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the next step for a designer would be to fix those violations

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there can be advanced ways of fixing these violations including ECO

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and other things but the most interesting thing is the fixing sometimes can be easy

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but what a good designer actually has to do is identify

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the patterns why these violations are happening why they're there in the first place

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so let me first enable all the metals again

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and we're going to zoom in on these violations one by one

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and see what's happening

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so we already did this one we saw it was a short there let's have a look at this one

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let's get rid of metal one and rid of four

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and five okay here's our violation it's not

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that far from the other one okay interesting let's look at this one here on the top

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here it is there's a pattern here and i'm not sure

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if you were able to see this right away but these violations

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that we have they're always next to a stripe

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this is a vdd stripe let's go back to the other ones

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you see here right next to a vdd stripe right next to a vss stripe

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this is somewhat natural

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because these stripes are really big pieces of metal they take a lot of routing resources

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so that zone becomes depleted of routing resources and violations can appear there

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but that's the pattern i was talking about once you identify the pattern fixing the drc is this relatively easy

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that being said we're going to stop this video here

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this is the end of the tutorial i'm planning on doing more advanced videos

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but for this tutorial this is it thank you

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Bu dersin kelimeleri ve konuşma notları

Bu konuşma dersi “Physical design tutorial with Cadence Innovus” videosuna dayanıyor. En çok tekrarlanan kelimeler: clock, metal, design, cell, tree. Bu videoda gölgeleme çalışması için 407 cümle ve 4911 kelime var. Konuşma bölümü 32:29 sürüyor. Konuşmacı dakikada yaklaşık 151 kelimeyle, günlük konuşmaya yakın doğal bir hızda konuşuyor. Kelimelerin yalnızca %81’i İngilizcede en sık kullanılan 3.000 kelime arasında, bu yüzden kelime dağarcığı zorlayıcı.

Bu videodaki önemli kelimeler

Videodan öğrenmeye değer 15 kelime, telaffuzu ve anlamıyla:

Kelime	Telaffuz	Anlam
placement isim	/ˈpleɪ̯smənt/	yerleştirme
wire isim	/ˈwaɪɚ/	tel
pin isim	/pɪn/	karfiçe
script isim	/skɹɪpt/	hat
horizontal sıfat	/ˌhoɹəˈzɑn.təl/	yatay
minimize fiil	/ˈmɪn.ɪˌmaɪz/	azaltmak, cüceleştirmek
layer isim	/ˈleɪ̯ɚ/	katman, tabaka
vertical sıfat	/ˈvɝ.tɪ.kəl/	dikey
delay isim	/dɪˈleɪ̯/	gecikme, rötar
notion isim	/ˈnoʊʃən/	fikir, kavram
canvas isim	/ˈkæn.vəs/	kanvas, tuval
designer isim	/dɪˈzaɪnɚ/	tasarımcı, dizayncı
density isim	/ˈdɛn.sə.ti/	yoğunluk
implementation isim	/ˌɪmplɪmənˈteɪʃən/	tatbik (obsolecent), uygulama
terminal isim	/ˈtɚmɪnəl/	terminal

Duyacağınız deyimsel fiiller

Kelime	Anlam
figure out fiil	açığa çıkarmak
put out fiil	çıkarmak
turn off fiil	kapamak

Tekrar etmeye değer cümleler

Videodan, günlük konuşmada yeniden kullanabileceğiniz kısa ve tam cümleler:

How do we get started?
What do you get after you initialize the design?
What do we have at this point?
How do we do that?
What are the components of the mesh that we're going to build?

Bu videodaki dil bilgisi

Konuşmacının en çok kullandığı yapılar, videodaki sözcüklerin aynısıyla:

Yapı	Videoda
Edilgen yapı be + fiilin üçüncü hâli — kimin yaptığı değil, ne olduğu önemli	is intended · is included · are provided
Present perfect have/has + fiilin üçüncü hâli — geçmişte olan ama şimdi de önemli olan bir eylem	haven't placed · have decided · has been

Dikkat edilecek telaffuzlar

Konuşmacı we're, I'm, gonna gibi kısaltılmış biçimleri 100 kez kullanıyor. Bunları duyduğunuz gibi kısa söyleyin.

“th” sesleri: synthesis /ˈsɪnθəsɪs/, width /ˈwɪtθ/, thick /θɪk/, underneath /ˌʌndɚˈniθ/
“sh” ve “zh” sesleri: violation /ˌvaɪ.əˈleɪ.ʃən/, notion /ˈnoʊʃən/, implementation /ˌɪmplɪmənˈteɪʃən/, mesh /mɛʃ/, dimension /daɪˈmɛn.ʃən/
Uzun kelimeler — vurguyu doğru yere koyun: violation /ˌvaɪ.əˈleɪ.ʃən/, horizontal /ˌhoɹəˈzɑn.təl/, implementation /ˌɪmplɪmənˈteɪʃən/, complicated /ˈkɑm.plɪˌkeɪ.tɪd/, incredibly /ɪŋˈkɹɛdɪbli/

Türkçe konuşanların zorlandığı sesler:

/w/ — dudaklar yuvarlak, /v/ değil: wire /ˈwaɪɚ/, width /ˈwɪtθ/, whatsoever /ˌ(h)wʌtsoʊˈɛvɚ/
Kelime başındaki ünsüz kümesi — araya ünlü eklemeyin: clock /klɑk/, placement /ˈpleɪ̯smənt/, stripe /stɹaɪp/, flip /flɪp/, script /skɹɪpt/
/æ/ — “e”den daha açık: valid /ˈvælɪd/, canvas /ˈkæn.vəs/, overlap /ˌəʊvəˈlæp/, abstract /ˈæbˌstɹækt/, variable [ˈvæɹ.i.ə.bl̩]

Bu videoyla nasıl çalışılır

Videonun tamamını konuşmadan bir kez dinleyin ve bilmediğiniz kelimeleri not edin.
0,75× hızla başlayın, cümle cümle tekrar edin ve kolaylaşınca normal hıza dönün.
Kendinizi kaydedin ve orijinaliyle karşılaştırın; placement, wire, pin gibi kelimelere özellikle dikkat edin.

Gölgeleme Tekniği Nedir?

Gölgeleme, başlangıçta profesyonel tercüman eğitimi için geliştirilen ve çok dilli Dr. Alexander Arguelles tarafından popüler hale getirilen, bilim destekli bir dil öğrenme tekniğidir. Yöntem basit ama güçlüdür: ana dili İngilizce olan bir sesi dinler ve hemen yüksek sesle tekrar edersiniz — konuşmacıyı 1-2 saniye gecikmeyle takip eden bir gölge gibi. Pasif dinleme veya dilbilgisi alıştırmalarının aksine, gölgeleme beyninizi ve ağız kaslarınızı gerçek konuşma kalıplarını eşzamanlı olarak işlemeye ve yeniden üretmeye zorlar. Araştırmalar, telaffuz doğruluğu, tonlama, ritim, bağlı konuşma, dinleme anlama ve konuşma akıcılığını önemli ölçüde geliştirdiğini göstermektedir — bu da onu IELTS Konuşma hazırlığı ve gerçek dünya İngilizce iletişimi için en etkili yöntemlerden biri yapar.

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Bu dersin kelimeleri ve konuşma notları

Bu videodaki önemli kelimeler

Duyacağınız deyimsel fiiller

Tekrar etmeye değer cümleler

Bu videodaki dil bilgisi

Dikkat edilecek telaffuzlar

Bu videoyla nasıl çalışılır

Gölgeleme Tekniği Nedir?