Shadowing Practice: How are Microchips Made? ๐ฅ๏ธ๐ ๏ธ CPU Manufacturing Process Steps - Learn English Speaking with Video
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Inside the smartphone are 62 microchips containing a total of 90 billion transistors.
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These microchips are incredibly powerful and the cornerstone of all technology.
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But how are billions of nanoscopic transistors manufactured into a microchip the size of a tiny ant?
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Well, all these microchips were manufactured in a semiconductor fabrication plant like this one.
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Inside it is a clean room which spans the area of eight football fields and is filled with hundreds of machines
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ranging in size from that of a van to
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that of a city bus and costing anywhere between a few million and 170 million dollars.
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Within this microchip factory silicon wafers travel from machine to machine and and undergo around a thousand processes over a three-month period.
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And, by the end of production, each silicon wafer will be covered in hundreds of CPU chips,
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each containing 26 billion transistors.
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When we zoom in, we can see the nanoscopic transistors at the bottom, and over a dozen layers of wires above.
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This integrated circuit is then cut out from the wafer, tested and packaged so that it can be installed into your desktop computer.
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In this video, we're going to explore the entire microchip manufacturing process
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and show you how billions of nanoscopic transistors
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and an impossibly complex 3D maze of wires are manufactured in one of the world's most technologically advanced microchip factories.
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It's an incredibly complicated process, So stick around and let's jump right in.
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A portion of this video is sponsored by Brilliant.org.
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There are two sides to understanding how microchip manufacturing works.
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The first is the sequence of steps and processes needed to build the nanoscopic transistors and the labyrinth of wires.
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Whereas the second is how the semiconductor fab and multi-million dollar equipment of the clean room floor work.
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And we'll be flipping between these two sides to get a complete picture.
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Let's start by opening up this desktop computer, focusing on the CPU and taking a look at what's inside.
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Here we have an integrated circuit, or die, which we'll refer to as a chip.
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This chip has 24 cores, a memory controller, a graphics processor and many other sections.
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Within one of the cores we can see its block diagram and the various elements.
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Zooming in on this multiply block, we find a layout of 44,000 transistors that physically execute 32-bit multiplication
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and constitute just .00017% of the overall 26 billion transistors in the CPU.
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Zooming in even further, we see layers of metal wires or interconnects, and at the very bottom are the transistors that form the basic logic gates.
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Note that these layers of metal interconnects aren't floating, but rather the empty space that you see is filled with insulating materials,
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thus providing structure and preventing the metal wire layers from touching.
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Furthermore, here we're only showing the transistors at the bottom and five layers of metal interconnects, with vias traveling vertically between the layers.
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In actuality, there are a total of 17 metal layers of wires in the CPU,
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and each successive set of levels uses larger and larger interconnects.
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At the bottom are local interconnects that move data around this 32-bit multiply circuit.
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In the middle are intermediate interconnects that move data around the core.
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And at the top are global interconnects that move data around the entire CPU.
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You might be wondering how small are these transistors.
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Zooming in again and past the interconnect layers,
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we find finfets, which are transistors whose channel dimensions are 36 by 6 by 52 nanometers,
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with a transistor-to-transistor pitch of 57 nanometers.
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Clearly the transistors are incredibly small.
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Here's a mitochondria, a dust particle, and a human hair for size comparisons.
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Now that you have a sense of what the transistors and labyrinth of metal interconnects look like, let's explore how they're manufactured.
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We'll begin with an analogy.
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Imagine baking a cake that's 80 layers tall, with each layer cut to a unique shape.
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To make this cake, there are 940 steps in the recipe,
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which takes three months to complete and and includes hundreds of exotic ingredients.
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And if any measurement, baking time, or temperature is more than 1% off, then the cake is entirely ruined.
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That's kind of what it's like to make a microchip.
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But microchips are even more complicated.
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Let's look at a single layer of this integrated circuit and run through a simplified set of steps used to build it.
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To start, a layer of insulating silicon dioxide is deposited on top of the wafer,
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and then a layer of light-sensitive photoresist is spread across the top.
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Next, using UV light and a stencil, a pattern is applied to the photoresist.
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Solvents then are used to remove the areas hit by the UV light, thus creating a patterned mask layer.
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Using the mask, the revealed silicon dioxide is etched away down to the previous layer.
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Next, the mask layer is removed
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and a layer of copper is added to cover the wafer and fill in the areas that were just etched away.
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Finally, the surface is ground down and leveled off to reveal the copper and insulator patterns.
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And thus, a single layer is completed.
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In order to build the next layer, which is a vertical set of metal vias, we repeat the same set of steps,
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but use a different pattern for the photomask.
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Since these layers are all built using the same set of steps,
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it's more effective to visualize the steps as a circle like a clock.
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To build all the 80 layers of the die,
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this sequence is repeated over and over, resulting in 940 steps.
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One important note is
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that the FinFET transistors at the bottom are even more complicated than the metal wires
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and thus additional steps are needed to fabricate them.
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Furthermore, cleaning the wafer to wash away dust particles that may have landed on the wafer,
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as well as inspecting the wafer to make sure everything is being built properly, happens frequently and these steps need to be added to the circle.
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A different tool is used to complete each of these process steps.
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Now that we have an understanding of the steps, let's take a look at this semiconductor fabrication plant.
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This CPU is manufactured on a 300 millimeter silicon wafer which can fit 230 CPU chips.
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In contrast, DRAM chips are considerably smaller and thus 952 of them can fit on a wafer.
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These silicon wafers are carried in stacks of 25 using a container called a front opening universal pod or foop.
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This sealed plastic wafer carrier is transported around the clean room floor using an overhead transport system
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which lowers the foop onto the tool's landing pad.
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Inside the tool, robotic arms transport the wafer through vacuum load locks and to different process chambers where materials are added,
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removed, or processed in ways that we'll explore later.
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The wafers are then returned to the foop, resealed inside, lifted up to the overhead transport system,
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and carried to and dropped onto the next tool, where the next step in the process is completed.
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To build the entire chip composed of 80 different layers, it takes three months of traveling from tool to tool,
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where at each stop one of the 940 process steps is completed.
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In order to increase the microchip mass production capabilities of a semiconductor fabrication plant,
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or fab, typically there are dozens of the same semiconductor tools tools organized in rows that perform the same process.
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On the clean room floor, there are a total of 435 semiconductor tools,
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resulting in the fab's production capacity of 50,000 wafers, or 11.5 million CPUs a month.
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These tools have rather complicated names, so we'll start by categorizing them according to their functionality.
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There are six groups, making the mask layer, adding material, removing material, modifying the material,
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cleaning the wafer, and finally inspecting the wafer.
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We've color-coded the different functional groups to the various tools and process steps to help you not get lost.
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Let's next look at each of these semiconductor tools and see how they process the wafer in various ways.
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We'll start with the ones that are used to make the mask layer or the nanoscopic stencil on the wafer.
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These tools include the PhotoResist Spin Coater, PhotoLithography Tool, Developer, and PhotoResist Stripper.
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First, the PhotoResist Spin Coater applies a light sensitive layer to the surface of the wafer
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and sends it through a soft bake where the wafer is heated in order to evaporate the solvent from the photoresist.
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Next, the wafer goes to the lithography tool, which shines UV light through a stencil, which is technically called a photomask.
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The light passes through the stencil and is then demagnified or shrunk down to produce a nanoscopic pattern on the wafer.
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Wherever the light from the stencil touches the wafer, the photoresist is weakened.
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The wafer then goes to the developer and the weakened photoresist is washed away,
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leaving only the patterned nanoscopic stencil on the wafer.
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The wafer is then sent through a hard bake to harden the remaining photoresist.
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Next, the wafer travels to other tools to undergo processing.
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And once these processes are completed, the wafer goes to a photoresist stripper,
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which uses solvents to dissolve and remove the photoresist mask layer.
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And that's how a mask layer is formed and then removed.
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The photolithography tool is one of the most important, so let's take a look at it.
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Inside is a UV light source, a set of lenses to focus the light,
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a photomask which contains the stencil or design of the layer to be patterned, and a wafer carrier.
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The photomask is 6 by 6 inches and, based on the dimensions of the CPU,
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can fit two copies of a single layer of the CPU design.
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The purpose of using a photomask with these crazy optics is
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because it's a reliable way to copy
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and paste a design for billions of nanoscopic transistors and wires onto 230 identical CPUs
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on a single wafer in a few minutes.
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After the light passes through the photo mask,
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the UV light goes to more lenses in order to shrink down the pattern by a factor of four
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and print a single layer of the design onto the photoresist.
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The wafer carrier steps from position to position,
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printing the photo mask image at each stop until all 230 chips are patterned.
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Let's clarify one detail.
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In our previous examples we talked a lot about this CPU having 80 layers.
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Specifically, what we were referring to is the number of photo masks
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and mask layers used to create all the different layers of patterns on the wafer.
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Therefore, one complete CPU chip uses 80 different photo masks, each costing $300,000.
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With only one mask layer being patterned at a time, this CPU chip will undergo 80 separate visits to the lithography tool.
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We could spend another hour talking about photolithography, but let's move on to the next category of tools.
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Deposition tools are used to add or deposit material onto the wafer.
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A lot of times we use the mask layer from the
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photolithography step to add materials to the areas uncovered by the mask layer, kind of like spray painting through a stencil.
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Due to the wide range of elements and compounds used to create the layers,
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deposition tools have a wide range of variations with complicated names and acronyms for each variant.
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But essentially, there are three key groups of materials that are added or deposited onto the wafer.
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Metals such as copper or tantalum, insulators which are typically called oxides, and crystalline layers of silicon.
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Each group of different materials uses different physics and chemistry principles to deposit the material on the wafer,
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and therefore has a different technical name for the tool that deposits the material.
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Deposition tools typically have a central wafer handling chamber, with the various chambers attached to the edges,
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each one dedicated to adding just a single element or compound.
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The next category of machines do the opposite, which is to remove material.
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There are two key methods.
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The first is etching.
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Etchers use either corrosive chemicals or high-energy plasmas to react with and remove materials from the surface of the wafer.
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They're typically used with the mask layer stencil in order to remove the material exposed by the mask,
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thus creating a hole that can be later filled by a deposition tool.
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The second method to remove material is CMP, which is chemical mechanical planarization.
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CMP applies slurry and uses abrasive pads to grind and polish away the top surface of the wafer, making it perfectly flat.
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CMP levels off the top layers of the wafer
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and is typically used as the last step in a cycle
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of processes in order to prepare the wafer for another layer to be added.
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The fourth category are tools that modify the silicon and are called ion implanters.
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These tools use the photomask stencil to bombard the unmasked regions with phosphor,
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boron, or other elements in order to make the P and the N regions required to form the transistors themselves.
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Therefore, ion implanters are only used in the front end of line.
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You might think that this is adding material.
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However, ion implanters only add around one atom of phosphor or boron for every 10,000 atoms of silicon.
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Additionally, while other machines spray paint a layer on top of the wafer, ion implanters hurl atoms deep into the silicon lattice,
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kind of like a cannon launching a baseball six feet into a concrete wall.
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This process typically damages the silicon lattice,
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which is why the following step is to repair the silicon by heating the wafer using a separate tool called an annealer.
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The fifth category of tools are used to clean and remove any contaminants or particles from the wafer.
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These wafer washers use ultra-pure water to clean the wafer and then dry it with nitrogen or hot isopropyl alcohol.
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Cleaning the wafer happens rather frequently in order to remove any stray particles that may have fallen onto the wafer.
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And finally, sixth, are tools that inspect the transistors and metal layers for defects and are called metrology tools.
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A common metrology tool uses a scanning electron microscope with nanometer
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level resolution to take pictures of the top surface of the wafer
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and determine if there are defects such as improperly patterned layers or particles on the surface.
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When fabricating an integrated circuit that takes three months to complete,
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it's important to repeatedly monitor the progress and make sure that each of the processes is being executed with nanometer level precision.
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Now that we've covered each of the categories, here are the color-coded process steps along with the layout of the tools the semiconductor fabrication plant.
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Let's run through the complete set of steps used to manufacture a single metal interconnect layer.
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First, a layer of insulating silicon dioxide is deposited onto the wafer.
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Next, photoresist is spread across the surface and the wafer is sent through a soft bake to remove the solvent.
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The wafer then travels to the photolithography tool, where the design from the photomask is transferred to each of
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the chips on the wafer by weakening the areas of photoresist hit by the light.
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The wafer next goes to the developer to wash away the sections
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that were hit by the light from the lithography tool and then through a hard bake to harden the remaining photoresist.
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With the mask layer built, the wafer goes to an etching tool,
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where a plasma etcher removes a vertical column through the exposed silicon dioxide until it reaches the previous layer's metal liars.
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Next, the wafer is sent to a photoresist stripper, where the mask layer is removed.
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The wafer then travels to a physical vapor deposition tool,
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where a sequence of metals fills in the exposed pattern and coats the wafer in metal.
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Finally, the wafer is sent to a chemical mechanical planarization tool, where the metal is ground down
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so that all that remains is a flat layer of insulating silicon dioxide
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and conductive copper interconnects that match the pattern from the photomask.
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A single metal layer is now completed, and the wafer is ready for the next cycle to begin,
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where insulating silicon dioxide in the vias will be added.
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Note that cleaning and wafer metrology or inspection steps occur in between many of these other steps.
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Furthermore, the process steps to make the transistors are less straightforward and utilize the ion implanter,
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and thus we'll cover them in a separate video on transistor physics and design.
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These steps are for building the integrated circuit on the wafer.
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However, there are additional steps in manufacturing a microchip, which we'll explore in a little bit.
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But before we get there, one important thing to note
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is that the semiconductor industry is incredibly secretive regarding the exact tool layout
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and the process steps and recipes used to make the transistors.
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We wanted to make the best video on how microchips are made,
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and it took us 180 hours of scouring the internet and textbooks for information and reference images.
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And, using what we found, we spent 205 hours modeling each of these tools,
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the many layers of the integrated circuit, and the semiconductor fab.
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Furthermore, writing the script took about 100 hours,
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and then animating all these visuals took more than 825 hours.
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As a result, this video took over 1300 hours to make, and it's entirely free to watch.
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We want to make more videos like this one, where we explore computer architecture and how transistors work,
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and we can't do it without your help.
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The best way you can help is by taking a few seconds to scroll down Write a comment below,
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like this video, subscribe if you haven't already, and then share this video on social media or send it to a friend or colleague.
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Truly, just a few seconds of your time helps far more than you think.
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Additionally, we have a Patreon page where we'll be releasing behind-the-scenes footage of our work and updates for upcoming videos.
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If you find what we do useful, we would appreciate any support.
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Thank you.
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So then, what are the additional steps in manufacturing a microchip?
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Before chip manufacturing at the fab, we first have to manufacture the silicon wafers by refining quartzite into pure silicon,
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and then growing a monocrystalline ingot and cutting it into wafers.
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For reference, these 300 millimeter wafers are around three quarters of a millimeter thick.
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They have a barcode on the side and a small notch in them to indicate the direction of the crystal lattice.
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Furthermore, these wafers are incredibly delicate and shatter into hundreds of shards when broken.
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A single wafer costs around $100.
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But after being populated with CPUs,
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it's worth closer to $100,000, making it quite literally 10 times more valuable than its weight in gold.
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Moving on to the steps after chip manufacturing.
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The completed wafer is sent to a separate building where each of the CPUs undergoes rigorous testing to figure out
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if it works as intended.
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If a CPU works, that's great.
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But frequently, a particle or photomass defect has damaged a section of the integrated circuit, rendering that section defective.
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These semi-functional circuits are then categorized or binned, based on what still works.
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These Intel 13th Gen processors are sold as an i9, i7, i5, or i3,
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depending on how many cores are functional with different product lines of CPUs whose onboard integrated graphics sections are defective.
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These wafers are transported to another building where the chips are cut out using a laser, flipped over and placed on an interposer,
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which distributes the connection points to a printed circuit board while a protective heat conductive cover is placed on the back side.
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The printed circuit board holds the landing grid array that interfaces with the motherboard as well as various electrical components.
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Next, an integrated heat spreader is mounted on top
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and the entire assembly is tested one last time before being packaged for sale.
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Finally, the CPU is now ready to be mounted onto the motherboard and installed into your desktop computer.
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It's important to understand that chip manufacturing requires an incredible amount of science
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and engineering and there's a free
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and easy way to learn the basic principles inside each of these complex tools and that's with this video's sponsor Brilliant.org.
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Microchip fabrication is a massive topic.
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And thus, we have two more equally complex videos that we're working on.
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The first will be an in-depth 3D animated factory tour and the second will explore transistor physics,
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FinFETs, and the next generation of transistors.
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We're also working on a series of videos on GPUs and a separate one on CPU architecture.
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Thanks for watching to the end.
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ืืืฆืจ ืืืืื ืืืขืจืืช ืืืืื ืืฉืืขืืจ ืืื
ืฉืืขืืจ ืืืืืืจ ืืื ืืจืื C1 ืืืืกืก ืขื ืืกืจืืื โHow are Microchips Made? ๐ฅ๏ธ๐ ๏ธ CPU Manufacturing Process Stepsโ. ืืืืืื ืฉืืืืจืืช ืืื ืืจืื: wafer, layer, tool, step, transistor. ืืกืจืืื ืืื ืืฉ 265 ืืฉืคืืื ื-3748 ืืืืื ืืชืจืืื Shadowing. ืืืืืืจ ื ืืฉื 27:47. ืืืืืจ ืฉืืืจ ืขื ืงืฆื ืืฆืื ืฉื ื-135 ืืืืื ืืืงื, ืงืฆื ื ืื ืืชืจืืื Shadowing. ืจืง 73% ืืืืืืื ื ืืฆืืืช ืืื 3,000 ืืืืืื ืื ืคืืฆืืช ืืืืชืจ ืืื ืืืืช, ืื ืฉืืืฆืจ ืืืืืื ืืืชืืจ.
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15 ืืืืืื ืืืชืงืืืืช ืืืืชืจ ืืกืจืืื, ืขื ืืืืืื ืืืืฉืืขืืช ืฉืืื:
| ืืืื | ืืืืื | ืืฉืืขืืช |
|---|---|---|
| wafer ืฉื ืขืฆื | /หweษชฬฏfษ/ | ืึธืคึถื, ืึทืคึฐืึธื |
| transistor ืฉื ืขืฆื | /tษนรฆnหzษชs.tษ/ | ืืจื ืืืกืืืจ |
| silicon ืฉื ืขืฆื | /หsษชlษหkษn/ | ืฆืืจื |
| stencil ืฉื ืขืฆื | /หstษnsษl/ | ืกึฐืึถื ึฐืกึดืื, ืฉึทืืึฐึผืืึนื ึธื |
| semiconductor ืฉื ืขืฆื | /หsษmikษnหdสktษ/ | ืืึนืึดืืึฐ ืึฐืึถืึฑืฆึธื |
| particle ืฉื ืขืฆื | /หpษษนtษk(ษ)l/ | ืึถืึฐืงึดืืง, ืึทืจืึดืืจ |
| bake ืคืืขื | /beษชk/ | ืึธืคึธื |
| insulate ืคืืขื | /หษชnsสleษชt/ | ืืืื, ืึดึผืึตึผื |
| lattice ืฉื ืขืฆื | /หlรฆt.ษชs/ | ืกืจืื, ืกืืื |
| lithography ืฉื ืขืฆื | /lษชฮธหษษกษนษfi/ | ืืืคืก ืืื |
| subscribe ืคืืขื | /sษbหskษนaษชb/ | ื ึดืึฐื ึธื |
| boron ืฉื ืขืฆื | /หbษหหษนษn/ | ืืืจืื, ืึผืึนืจ |
| labyrinth ืฉื ืขืฆื | /หlรฆb.ษ.ษนษชnฮธ/ | ืึธืืึนืึฐ, ืึธืึดึผืืจึดืื ึฐืช |
| phosphorus ืฉื ืขืฆื | /หfษs.fษ.ษs/ | ืืจืื |
| weaken ืคืืขื | /หwikษn/ | ืืืืืฉ |
Phrasal verbs ืฉืชืฉืืขื
| ืืืื | ืืฉืืขืืช |
|---|---|
| figure out ืคืืขื | ืึตืึดืื, ืืฆื ืชืฉืืื |
ืืงืืืง ืืกืจืืื ืืื
ืืืื ืื ืฉืืืืืจ ืืฉืชืืฉ ืืื ืืื ืืจืื, ืขื ืืืืืื ืืืืืืงืืช ืืืกืจืืื:
| ืืื ื | ืืกืจืืื |
|---|---|
| ืกืืื (Passive voice) be + past participle โ ืืืืฉ ืืื ืขื ืื ืฉืงืืจื, ืื ืขื ืื ืฉืขืืฉื ืืช ืืคืขืืื | were manufactured ยท is filled ยท will be covered |
| ืืฉืคืื ืืืงื (Relative clauses) who / which + clause โ ืืืืข ื ืืกืฃ ืขื ืืื ืื ืืืจ | finfets, which are ยท layer, which is ยท wafer which can |
| ืืืื ืืืฉืื (Present perfect) have/has + past participle โ ืคืขืืื ืฉืงืจืชื ืืขืืจ ืืขืืืื ืืฉ ืื ืืฉืืืืช ืื ืืฉืคืขื ืขืืฉืื | we've covered ยท has damaged |
ืืืืื ืฉืฉืืื ืืฉืื ืื ืืืื
ืืืืืจ ืืฉืชืืฉ ื-26 ืงืืฆืืจืื ืืฆืืจืืช ืืงืืฆืจืืช, ืืื we'll, we're, they're. ืืืจื ืืืชื ืืฆืืจื ืืงืฆืจื, ืืคื ืฉืืชื ืฉืืืขืื ืืืชื.
- ืืฆืืืืื ืฉื โthโ: lithography /lษชฮธหษษกษนษfi/, labyrinth /หlรฆb.ษ.ษนษชnฮธ/, motherboard /หmสรฐษหbษษนd/
- ืืฆืืืืื ืฉื โshโ ื-โzhโ: fabrication /fรฆbษนษชหkeษชสษn/, deposition /หdษp.ษหzษชส.ษn/, dimension /daษชหmษn.สษn/
- ืืืืื ืืจืืืืช โ ืฉืืื ืื ืืืืขืื: interconnect /หษชn.tษ.kษหnษkt/, semiconductor /หsษmikษnหdสktษ/, fabrication /fรฆbษนษชหkeษชสษn/, deposition /หdษp.ษหzษชส.ษn/, lithography /lษชฮธหษษกษนษfi/
ืฆืืืืื ืฉืืืืจื ืขืืจืืช ืืชืงืฉืื ืืื:
- /w/ โ ืฉืคืชืืื ืืขืืืืืช, ืื /v/: wafer /หweษชฬฏfษ/, weaken /หwikษn/
- /รฆ/ โ ืคืชืื ืืืชืจ ืื-โืึถโ ืืขืืจืืช, ืื ืืื โaโ ื-โcupโ: transistor /tษนรฆnหzษชs.tษ/, fabrication /fรฆbษนษชหkeษชสษn/, lattice /หlรฆt.ษชs/, labyrinth /หlรฆb.ษ.ษนษชnฮธ/, nanometre /หnรฆnoสหmitษr/
- /r/ โ ืืืฉืื ืื ื ืืืขืช ืืฉืื ืืงืื, ืื ื-โืจโ ืืืจืื ืืช: transistor /tษนรฆnหzษชs.tษ/, microchip /หmaษชkษนoสหtอกสษชp/, integrate /หษชn.tษช.ษกษนeษชt/, particle /หpษษนtษk(ษ)l/, fabrication /fรฆbษนษชหkeษชสษn/
ืืื ืืชืจืื ืขื ืืกืจืืื ืืื
- ืืงืฉืืื ืืื ืืกืจืืื ืคืขื ืืืช ืืื ืืืืจ, ืืจืฉืื ืืช ืืืืืื ืฉืืชื ืื ืืืืจืื.
- ืชืจืืื Shadowing ืืฉืคื ืืืจ ืืฉืคื ืืืืืจืืช ืจืืืื, ืืืืจื ืขื ืื ืืฉืคื ืขื ืฉืืงืฆื ืฉืืื ืชืืื ืืช ืืืืืจ.
- ืืงืืืื ืืช ืขืฆืืื ืืืฉืื ืืืงืืจ, ืชืื ืชืฉืืืช ืื ืืืืืื ืืื wafer, transistor, silicon.
ืืื ืืื ืืงืช ืืฉืืืืืื ื?
ืฉืืืืืื ื ืืื ืืื ืืงืช ืืืืืช ืฉืคื ืืืืกืกืช ืืืข ืฉืคืืชืื ืืืงืืจ ืืืืฉืจืช ืืชืืจืืื ืื ืืงืฆืืขืืื ืืคืืคืืืจืืช ืขื ืืื ืืคืืืืืืื ื"ืจ ืืืืกื ืืจ ืืจืืืืืก. ืืฉืืื ืคืฉืืื ืื ืขืืฆืืชืืช: ืืชื ืืงืฉืื ืืืืืื ืืื ืืืืช ืืืืืืช ืืืืืจ ืขืืื ืืงืื ืจื ืืื โ ืืื ืฆื ืืขืืงื ืืืจื ืืืืืจ ืขื ืขืืืื ืฉื 1โ2 ืฉื ืืืช ืืืื. ืื ืืืื ืืืืื ื ืคืกืืืืช ืื ืชืจืืืื ืืงืืืง, ืฉืืืืืื ื ืืืจืื ืืช ืืืื ืืืฉืจืืจืื ืืคื ืืขืื ืืืฉืืืจ ืืคืืกื ืืืืืจ ืืืืชืืื ืื ืืื ืืช. ืืืงืจืื ืืจืืื ืฉืื ืืฉืคืจ ืืฉืืขืืชืืช ืืช ืืืืง ืืืืืื, ืืืื ืืื ืฆืื, ืืงืฆื, ืืืืืืจ ืืืืืืจ, ืืื ืช ืืฉืืืขื ืืฉืืฃ ืืืืืืจ โ ืื ืฉืืืคื ืืืชื ืืืืช ืืฉืืืืช ืืืขืืืืช ืืืืชืจ ืืืื ื ืIELTS Speaking ืืืชืงืฉืืจืช ืืื ืืืืช ืืขืืื ืืืืืชื.